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  • Sequence in UVM

Sequence in UVM

UVM 6654
#sequence 39 #uvm 278 #interface 10 wait statement 4 @(posedge clk) begin 1
om30
om30
Full Access
19 posts
April 22, 2020 at 4:28 am

Hi,
I am new to UVM.
Can anyone help me in making sequence from this task which was in interface of my sv code.

  task automatic reg_read_lane (input [`NB_LANES-1:0] lane, input [ADDR_WIDTH -1:0] addr, output [DATA_WIDTH -1:0] data);
    begin
      wait(busy_flag == 1'b0); 
      busy_flag = 1'b1 ; 
      wait(psel[lane]==1'b0);
      @(negedge pclk[lane]);
      psel   [lane] = 1'b1;
      penable[lane] = 1'b1;
      paddr  [ADDR_WIDTH_EXT * lane + (ADDR_WIDTH_EXT -1) -:ADDR_WIDTH_EXT]  = {32'h0,addr};
      pwdata [DATA_WIDTH_EXT * lane + (DATA_WIDTH_EXT -1) -:DATA_WIDTH_EXT]  = {32'h0};
      pwrite [lane] = 1'b0;
      wait(pready[lane]);
      @(posedge pclk[lane]);
      data_int = prdata[DATA_WIDTH_EXT * lane + (DATA_WIDTH_EXT -1) -: DATA_WIDTH_EXT];
      data     = data_int  [15:0];
 
      if(pslverr[lane]) begin
        `uvm_info(pcs_interface,$psprintf("@%0h ERROR : Error resp received from apb slave ",addr),UVM_DEBUG)
        ->error_rsp_rcvd;
      end
      if($isunknown(data)) begin
        ->error_rsp_rcvd;
        `uvm_info(pcs_interface,$psprintf("@%0h ERROR : Unknown value detected for prdata",addr),UVM_DEBUG)
      end
      @(negedge pclk[lane]);
      psel   [lane] = 1'b0;
      penable[lane] = 1'b0;
      paddr  [lane] = 10'h00;
      pwdata [lane] = 8'h00;
      pwrite [lane] = 1'b0;
      busy_flag     = 1'b0; 
    end
  endtask : reg_read_lane

I am having confusion that can I put wait statement in sequence class or how to implement a sequence class like above.

Thank You in Advance

Replies

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chr_sue
chr_sue
Full Access
3846 posts
April 22, 2020 at 4:53 am

In reply to om30:

I believe you have a wrong understanding of a sequence. A sequence defines how seq_items wil be generated.
The code you are posting seems to be a mixture of code from your SV interface and your driver.
The PRDATA can be detected in your driver.
It is confusing what you are doing with the events.

om30
om30
Full Access
19 posts
April 22, 2020 at 5:23 am

Hi chr_sue,
The code which I had posted is a task in my interface of sv testbench code which now I am trying to convert into a UVM testbench code.
Here my requirement is that I want to do register read write operation for particular testcase so in my sv testbench I am providing addr and data to this task of interface and doing register read write operation but in UVM as I can't drive anything from testcase I am planning to make a sequence of register read and register write which will be driven by driver so there won't be any interface into my testcase of uvm.

chr_sue
chr_sue
Full Access
3846 posts
April 22, 2020 at 8:06 am

In reply to om30:

You cannot simply convert your SV code into UVM cide. The UVM has a certain structure and you have to follow this structure. The UVM testbench is constructed of agents. Each agent has inside a sequencer, a driver and a monitor (active agent). All these components are class-base. The UVM is heavily employing TLM. This requires working with seq_items. For simplifying the access to DUT regsietrs the UVM has a RAL which mirrors all your DUT registers in the testbench. These are only a very few aspects you have to consider.

om30
om30
Full Access
19 posts
April 22, 2020 at 10:08 am

Yes Sir I agree with you that sv code cannot be simply converted to uvm.
So I had developed whole testbench structure which is required for uvm i.e. active agent having driver, sequncer and monitor also scoreboard and environment. Everything is properly working with compilation clean. Now when I started writing testcase I got stuck into this thing as in sv code I was driving addr and data values from this task of interface which I had posted.

So now simply I just want to make a sequence through which register read write can be done without going into RAL as I am new to UVM.

chr_sue
chr_sue
Full Access
3846 posts
April 22, 2020 at 11:02 am

In reply to om30:

You have to define a seq_item which contains as data members the access type (read, write), addr and write data and read data.
In the sequence you are defining how you want to access your virtual interface, doing bus cycles for read and write.
In the test you are starting this sequence on the corresponding sequencer. That's it.

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