Sequence for Register Write and Read Check

Hi,

I am not using the RAL model for Register Rd-Wr and POR check.
I have created my own processor based Wr and read task (hooked Processor Vip). and i want to create one sequence to verify all the registers of one blocks.

Dummy Code :

virtual task body();
int data ;
for (i= 0 ; i<= 4; i++)
begin
if (i == 0)
data = 'hffffffff;
else if (i == 1)
data = 'hAAAAAAAA;
else if (i == 2)
data = 'h55555555;
else
data = 'h00000000;

  master_write(.addr(`REG_OFFSET_1 ), .data(data), .delay('h8), .len('h2), ........));
  master_read(.addr(`REG_OFFSET_1 ),  .delay('h8), .len('h2), ........);

 master_write(.addr(`REG_OFFSET_2 ), .data(data), .delay('h8), .len('h2), ........));
 master_read(.addr(`REG_OFFSET_2 ),  .delay('h8), .len('h2), ........);

master_write(.addr(`REG_OFFSET_3 ), .data(data), .delay('h8), .len('h2), ........));
master_read(.addr(`REG_OFFSET_3 ),  .delay('h8), .len('h2), ........);
end

.......
 ........

endtask

Could anyone suggest me the better way to verify the same thing ?

In reply to rupeshblr:

Why do you not want to use the RAL model? It makes things significantly easier and contains automated sequences for testing.

In reply to cgales:

dont have any specific reason. I know , Using RAL its easier.

But still it will be vey helpful if you suggest anything other than RAL

In reply to rupeshblr:

I do not know how many registers you have. If it is as mall number it is not useful to employ the RAL.
The code you are showing is very simple. ou do not work with randomized data. But this is necessary.
I recommedn the following solution.
Declare in your sequence an associative array. When writing to a certain register with a specific address you are storing the write value also in the associative array. When reading you are putting back a response from the driver with the read value. You can now compare with the written value from the assoc. array.