Hi,
I am not using the RAL model for Register Rd-Wr and POR check.
I have created my own processor based Wr and read task (hooked Processor Vip). and i want to create one sequence to verify all the registers of one blocks.
Dummy Code :
virtual task body();
int data ;
for (i= 0 ; i<= 4; i++)
begin
if (i == 0)
data = 'hffffffff;
else if (i == 1)
data = 'hAAAAAAAA;
else if (i == 2)
data = 'h55555555;
else
data = 'h00000000;
master_write(.addr(`REG_OFFSET_1 ), .data(data), .delay('h8), .len('h2), ........));
master_read(.addr(`REG_OFFSET_1 ), .delay('h8), .len('h2), ........);
master_write(.addr(`REG_OFFSET_2 ), .data(data), .delay('h8), .len('h2), ........));
master_read(.addr(`REG_OFFSET_2 ), .delay('h8), .len('h2), ........);
master_write(.addr(`REG_OFFSET_3 ), .data(data), .delay('h8), .len('h2), ........));
master_read(.addr(`REG_OFFSET_3 ), .delay('h8), .len('h2), ........);
end
.......
........
endtask
Could anyone suggest me the better way to verify the same thing ?