Sequence Overriding

UVM
1

Hi,

Suppose this is my test class-
########################################################################
class sot_test extends uvm_test;

`uvm_component_utils(sot_test)

sot_env m_env;

function new(string name = “sot_test”, uvm_component parent = null);
super.new(name, parent);
endfunction

//
// The build method of a test class:
//
// Inheritance:
//
// a_seq ← b_seq ← c_seq
//
function void build_phase(uvm_phase phase);
m_env = sot_env::type_id::create(“m_env”, this);
// Set type override
b_seq::type_id::set_type_override(c_seq::get_type());
// Set instance override - Note the “path” argument see the line for s_a creation
// in the run method
a_seq::type_id::set_inst_override(c_seq::get_type(), “bob.s_a”);
endfunction: build_phase

//
// Run method
//
task run_phase(uvm_phase phase);
a_seq s_a; // Base type
b_seq s_b; // b_seq extends a_seq
c_seq s_c; // c_seq extends b_seq

// Instance name is “s_a” - first argument,
// path name is “bob” but is more usually get_full_name() - third argument
s_a = a_seq::type_id::create(“s_a”,“bob”);
// More usual create call
s_b = b_seq::type_id::create(“s_b”);
s_c = c_seq::type_id::create(“s_c”);

phase.raise_objection(this, “starting test”);
s_a.start(m_env.m_a_agent.m_sequencer); // Results in c_seq being executed
s_b.start(m_env.m_a_agent.m_sequencer); // Results in c_seq being executed
s_c.start(m_env.m_a_agent.m_sequencer);
phase.drop_objection(this, “finishing_test”);

endtask: run_phase

endclass: sot_test

##################################################################################
Error-[SV-EEM-SRE] Scope resolution error
my_test.sv, 22
$unit, “b_seq::type_id::set_type_override”
Target for scope resolution operator does not exist. Token ‘b_seq’ is not a
class/package. Originating module ‘$unit’.
Check that class or package exists with referred token as the name.

My problem is how in build phase the test class will get the b_seq.
This code is taken from this place only UVM EXAMPLE CODE Plz check once and suggest the approch to solve this.

Thanks,
Sayam Raja

2

In reply to SAYAM RAJA:

You are mixing differnt things.
(1) build_phase, connect_phase are used to create/connect the UVM testbench.
(2) sequences are not part of the UVM topology. They are transient objects.
(3) In the build_phase of your test you are doing the override. And in the run_phase you are creating your sequence objects. The error message is correct.

3

Hi,

It seems that the error that you get is on this line, no?
b_seq::type_id::set_type_override(c_seq::get_type());

I think that the compiler tells you that it doesn’t recognize b_seq as a class. Did you forget to import its package by any chance? or that if both sot_test and b_seq are in the same package you may have their order reversed?

example of a reversed order is:
package xxx;
include "sot_test.svh" //this will lead to an error since b_seq is not introduced yet. include “b_seq.svh”
endpackage