Sequence item

Hi ,

In the below code , it is working fine without the object registration with the factory,
but showing error with the object registration. for every components and object we have to do factory registration right then why factory registration is showing error for uvm_sequence_item.

can anyone explain this.?

class and_trans extends uvm_sequence_item;
`uvm_object_utils(and_trans)

rand bit a;
rand bit b;
bit c;

function new(string name=“”);
super.new(name);
endfunction

uvm_object_utils_begin(and_trans) uvm_field_int(a,UVM_ALL_ON)
uvm_field_int(b,UVM_ALL_ON) uvm_field_int(c,UVM_ALL_ON)
`uvm_object_utils_end

endclass : and_trans

uvm_object_utils_begin(and_trans) | ncvlog: *E,DUPIDN (../env/and_trans.sv,14|34): identifier 'type_id' previously declared [12.5(IEEE)]. uvm_object_utils_begin(and_trans)
|
ncvlog: *E,DUPIDN (…/env/and_trans.sv,14|34): identifier ‘get_type’ previously declared [12.5(IEEE)].
uvm_object_utils_begin(and_trans) | ncvlog: *E,DUPIDN (../env/and_trans.sv,14|34): identifier 'get_object_type' previously declared [12.5(IEEE)]. uvm_object_utils_begin(and_trans)
|
ncvlog: *E,DUPIDN (…/env/and_trans.sv,14|34): identifier ‘create’ previously declared [12.5(IEEE)].

Thanks,
Sandeep Gaur R

In reply to Sandeep Gaur:

As your simulator says, you are registering the seq_item twice with the factory.
Please be adviced it is not recommended to use the field macros. Your code should look like this:

class and_trans extends uvm_sequence_item;
  `uvm_object_utils(and_trans)

  rand bit a;
  rand bit b;
  bit c;

  function new(string name="");
    super.new(name);
  endfunction

endclass : and_trans

In reply to chr_sue:

Got it Thanks,
But without using the field macros , how it will know whether it is used to compare or not.
using field macros we can provide the following access to the variables.
UVM_COMPARE,UVM_NO_COMPARE etc…

In reply to Sandeep Gaur:

You can make your own implementations, overriding what is provided by the field macros. Using a UVM FRamework Generator makes this work for you.

In reply to chr_sue:

ok Thanks…

In reply to Sandeep Gaur:

Here in the above code, you are actually registering the ‘and_trans’ item twice with the factory that’s why you’re getting those error.
1st time just after the class template and 2nd time after the constructor.

You can use one at a time of the below registration syntax depending on your requirement.

1)uvm_object_utils(and_trans) //This is class registration with the factory or 2)uvm_object_utils_begin(and_trans) //This is class registration with the factory+field automation macros
uvm_field_int(a,UVM_ALL_ON) uvm_field_int(b,UVM_ALL_ON)
uvm_field_int(c,UVM_ALL_ON) uvm_object_utils_end

In reply to Shipra_s:

Now I am Cleared about it…Thanks for your reply Shipra…

In reply to chr_sue:

Why is it not recommended to use field macros?

Thanks
Hayk

In reply to haykp:
Field macros are adding overhead to yout verification environment. Please see the details here:
https://verificationacademy.com/cookbook/uvm/performance-guidelines