Selecting a sequence in controlled form from large number of sequences..?

I have around 100 (or it can be more) sequences. I want to run this sequence in protocol specific manner whichever is required. I am thinking of using sequence library. Can anyone please suggest me proper way to achieve this…

In reply to RAGHURAJA:

With UVM-1.2 the sequence library construct is part of the UVM standard. It has 2 aspects. Firstly it as a structure to organize sequences belonging together. secondly it simplifies the handling of sequences belonging together. You can execute a sequence libaray like a sequence.
The definition looks like this:
class my_seq_lib extends uvm_sequence_library #(my_item);
uvm_object_utils(my_seq_lib) uvm_sequence_library_utils(my_seq_lib)
function new(string name=“”);
super.new(name);
init_sequence_library();
endfunction

endclass

For adding, getting and removing sequences from the library see the UVM Refernece Manual 1.2.

In reply to chr_sue:

Thanks or reply. Do we have any other way to do this without library…?

In reply to RAGHURAJA:
The question is how your sequences look like. The standard way is to define for each test a corresponding sequence. And you are executing the sequnce by starting this test. Be careful defining your sequences. Sequences execution should not end up in deterministic tests. Use the power of randomization.

Hi,

Write a uvm_component which will handle the protocol part. Connect this component with the monitors. So you can start the appropriate sequence depending upon the conditions. I hope this help you.

Regards
Saravanan

In reply to saravanantvs:
One of the key features is the separation of test from the testbench. In the test you are constructing the testbench which is customized to the needs of this test. And you are selecting the sequence which contains the functionality for this test. Of course you are doing somthing else like passing the virtual interface and configuration data to testbench components.
Typically I’m using a test base class which is doing all the things relevant for all tests and a specific test class which extends the test base class. See an example below:
//-----------------------------------------------------------------------------
class example_top_base_test extends uvm_test;
//-----------------------------------------------------------------------------

`uvm_component_utils(example_top_base_test)

apb_config apb_cfg;
spi_config spi_cfg;

example_top_config cfg;

example_top_env env;

extern function new(string name = “example_top_base_test”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);

endclass : example_top_base_test
//---------------------------------------------------------------------------
// Implementation
//---------------------------------------------------------------------------

function example_top_base_test::new(string name = “example_top_base_test”, uvm_component parent = null);
super.new(name, parent);
endfunction : new

function void example_top_base_test::build_phase(uvm_phase phase);
super.build_phase(phase);
// Create top config
cfg = example_top_config::type_id::create(“cfg”);
// Create sub config
apb_cfg = apb_config::type_id::create(“apb_cfg”);
spi_cfg = spi_config::type_id::create(“spi_cfg”);

if(!uvm_config_db #(virtual apb_if)::get(this, “”, “apb_if_i”, apb_cfg.vif))
`uvm_error(get_type_name(), “no virtual interface found”)

if(!uvm_config_db #(virtual spi_if)::get(this, “”, “spi_if_i”, spi_cfg.vif))
`uvm_error(get_type_name(), “no virtual interface found”)

cfg.apb_cfg = apb_cfg;
cfg.spi_cfg = spi_cfg;

uvm_config_db #(example_top_config)::set(this, “env”, “example_top_config”, cfg);

// Create env
env = example_top_env::type_id::create(“env”, this);

endfunction : build_phase

And her ea specific test:
//-----------------------------------------------------------------------------
class example_top_test1 extends example_top_base_test;
//-----------------------------------------------------------------------------

`uvm_component_utils(example_top_test1)

extern function new(string name = “example_top_test1”, uvm_component parent = null);
extern virtual function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
//---------------------------------------------------------------------------
// constraints
//---------------------------------------------------------------------------

endclass : example_top_test1
//---------------------------------------------------------------------------

function example_top_test1::new(string name = “example_top_test1”, uvm_component parent = null);
super.new(name,parent);
endfunction : new

function void example_top_test1::build_phase(uvm_phase phase);
uvm_config_db#(int)::set(this, “env.apb_env_i.agent”, “is_active”, UVM_ACTIVE);
uvm_config_db#(int)::set(this, “env.spi_env_i.agent”, “is_active”, UVM_ACTIVE);
super.build_phase(phase);
endfunction : build_phase

task example_top_test1::run_phase(uvm_phase phase);
example_top_default_seq vseq = example_top_default_seq::type_id::create(“vseq”);
phase.raise_objection(this, “Starting virtual sequence”);
uvm_info(get_type_name(), "Objection raised", UVM_MEDIUM) vseq.start(null); phase.drop_objection(this, "Finished virtual sequence"); uvm_info(get_type_name(), “Objection dropped”, UVM_MEDIUM)
endtask : run_phase

The virtual sequence looks like this:
class example_top_default_seq extends example_top_base_seq;

`uvm_object_utils(example_top_default_seq)

// UVC sequences
apb_default_seq apb_seq;
spi_default_seq spi_seq;

extern function new(string name = “example_top_default_seq”);
extern task body();

endclass : example_top_default_seq

Here iis the body task implementation:
task example_top_default_seq::body();
super.body();

apb_seq = apb_default_seq::type_id::create(“apb_seq”);
spi_seq = spi_default_seq::type_id::create(“spi_seq”);

`uvm_info(get_type_name(),“default sequence starting”, UVM_MEDIUM)

repeat(10) begin
`uvm_info(get_type_name(),“apb sequence starting”, UVM_MEDIUM)

void’(apb_seq.randomize());
apb_seq.start(apb_sequencer_i);
`uvm_info(get_type_name(),“spi sequence starting”, UVM_MEDIUM)

void’(spi_seq.randomize());
spi_seq.start(spi_sequencer_i);
end
`uvm_info(get_type_name(),“default sequence completed”,UVM_MEDIUM)
endtask : body

Hope this helps to answer your question.

In reply to saravanantvs:

Can you please elaborate @saravanan