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  • Scope resolution operator ::

Scope resolution operator ::

UVM 6753
#uvm 278 #systemverilog 102 Randomization Scope... 1
xfinity
xfinity
Full Access
52 posts
August 04, 2020 at 4:34 pm

Hi

class mxsclk_ver0_sequence #(type T=sys::mxsclk_ver0_params) extends uvm_sequence #(mxsclk_ver0_seq_item_base);
typedef T::clock_type_t     clk_cntrl_type_t;
mxsres_ver0_pin_mode_seq #(sys::mxs_vmxsres_vip)           mxsres_seq;
 
mxsres_seq.reset_pins       = {sys::mxsmif_vmxsres_vip::ACTIVE_RESET0,sys::mxs_vmxsres_vip::DEEPSLEEP_RESET0};

Can anyone explain how :: operator works here;

Did not understand these set of lines

Thanks

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dave_59
dave_59
Forum Moderator
10909 posts
August 04, 2020 at 8:18 pm

In reply to tejasakulu:

It's hard to explain without see how everything is defined. I'm assuming sys:: is reference to a package, and the others are references static members of class types as opposed to instance specific objects.

— Dave Rich, Verification Architect, Siemens EDA

Juhi_Patel
Juhi_Patel
Forum Access
95 posts
August 05, 2020 at 11:15 am

typedef T::clock_type_t clk_cntrl_type_t; This might be representing variable of type clock_type_t declared inside class T.

mxsres_ver0_pin_mode_seq #(sys::mxs_vmxsres_vip) mxsres_seq; This might be reference to sys::mxs_vmxsres_vip which will be transaction. 

mxsres_seq.reset_pins       = {sys::mxsmif_vmxsres_vip::ACTIVE_RESET0,sys::mxs_vmxsres_vip::DEEPSLEEP_RESET0};
according to general practice, Enums are declared in capital. so, It might be some enum declared inside sys::mxs_vmxsres_vip class.

This are some points drawn as per general understanding.

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