Sampling RTL outputs from different clock domain

I am working on a UVM TB. I have a below scenario:
RTL has 2 clocks, clk(system clock) and spi_clock. spi_clk is derived from clk. clk is 4 times faster than spi_clk.

  1. Input and output data are in sync with spi_clk. They are the main interface signals. So,my clocking block works on spi_clk. seq_item just has mosi_in input data and sr_data output data from RTL. Driver drives mosi_in input data and the monitor samples output data. Scoreboard checks data integrity. Things are all working fine.
  2. RTL generates some status signals at the end of the frame and these signals are generated in sync with clk, (system clock) which is faster than spi_clk. I need to capture/sample these signals and validate them.
    What is the best way to do it?
    I have some thoughts:
    1.I plan to have another clocking block with clk and these output signals will be clockvars for this?
  3. Can i have another seq_item type which will just have these signals? Since i don’t have anything to drive w.r.t clk, can i just sample those RTL signals in the monitor(another monitor) on every clock?
    Eg;(i have not yet coded anything)
    In the monitor:
    @(vif.cb);
    seq_item_collected.rtl_output1= vif.cb.rtl_output1;

something like above?
3. I need to have a passive agent with just a monitor to sample these output signals and pass them to scoreboard, right?
4. How do i sync the output data( that is in sync spi_clk) and these output signals on TB side, since i need to validate these signals based on the output data.

Please give some inputs or some links to go further.
Tank you!

In reply to uvmsd:
You are talking only about different clocks. What I’m missing is how many different functional interfaces does your RTL have. I guess it is at least 1, i.e… spi interface.
But there might be a second one…
Please explain.

In reply to chr_sue:

@chr_sue,
There is just one interface, SPI interface. Spi data comes as frames into the RTL. RTL generates some status signals at the end of the frame, based on the frame data. And these status signals are generated on clk(system clock) whereas spi input/output data is processed on spi_clk. And also these signals are high for just one clk. I need to capture and validate.
Hope it’s clear now.

In reply to uvmsd:

In my eyes you have 2 functional interfaces,1 is the spi and the other one is synchronized on system clk and generates only some outputs.
The spi interface is active and the 2nd interface is passive.

In reply to chr_sue:

Yes.
Are my points in first message hold good?

In reply to chr_sue:

In reply to uvmsd:
In my eyes you have 2 functional interfaces,1 is the spi and the other one is synchronized on system clk and generates only some outputs.
The spi interface is active and the 2nd interface is passive.

Do i have to mention/configure this new agent to be passive agent anywhere? I dont have to, right? since it just hasa monitor and I don’t have to check ‘get_is_active’ anywhere.

In reply to uvmsd:

The additional agent has to be active, because you do not have inputs to this interface.
You can do this from the test, configuring this agent as ‘UVM_PASSIVE’ or you can implement your agent as passive, having no sequencer/driver inside.

In reply to chr_sue:

In reply to uvmsd:
The additional agent has to be active, because you do not have inputs to this interface.
You can do this from the test, configuring this agent as ‘UVM_PASSIVE’ or you can implement your agent as passive, having no sequencer/driver inside.

@chr_sue,
your first sentence is bit confusing. Did you want to say, ‘additional agent has to be passive’?

Anyway, I have implemented my agent as passive. It just has a seq_item(for those status signals) and monitor. There is no sequencer/driver.
I just sample the status signals in monitor through interface/clocking block.

My understanding is that, when i run a test, I get to sample outputs in both the agetns though inputs are sent only to agent1.

  1. Agent1 - active. Inputs driven and outputs sampled on spi clk.
  2. Agent2 - passive. Output status signals sampled on clk.

In reply to uvmsd:

You are right. The additional agent ha to be passive as.

In reply to uvmsd:

To be honest I dont see here the reason of implementing separate agent.

You have some error,status check signals which are generated by fast clock and output signals which are generated by slow clock: spi_clock. So why not use monitor-scorebaord for all this.
Monitor can read at first the status signals by fast clock and using another fork/join thread read the output signals coming from slow-clock.
Than make a transaction and send all this to scoreboard for checking ( more close to your 2nd point).

The drawback of having separate passive agent here, is following :
a) Imagine the case when the status signals is telling that generated output data is wrong. So how you gonna explain monitor/scoreboard that no need to collect/compare input/output data and increase error counter.
-) of course this is possible, but you need to write extra code here.
b) what if in future some of the status signals will be generated by slow clock.

In reply to haykp:

@haykp , thanks for your inputs. I have already implemented a passive agent. Still, will keep your point in mind.
I have few questions:

“Monitor can read at first the status signals by fast clock and using another fork/join thread read the output signals coming from slow-clock.
Than make a transaction and send all this to scoreboard for checking ( more close to your 2nd point).”

Please note that, though the status signals are on faster clock, I need to sample them at the end of the data collection/sampling(which is with slower clock).
Did you say something below in monitor?

fork 
forever begin
  @(fast_clock);
   //sample the status signals
end
forever begin
  @(slow_clock)
  //sample the data
end
join 

I am not sure if i could combine them into a single sequence item and write into TLM fifo since scoreboard too generates these status signals based on the data collected.