RUVM: few kinds of backdoor access

UVM
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1

As in the topic, does RUVM4.6 support few kinds of backdoor access?

I would like to reuse the verification environment for RTL and gatelevel verification of a certain DUT. I have a problem with backdoor access through the register model. The RTL and gatelevel floavor of the DUT requires slightly different backdoor hdl_paths:

  • in RTL the registers are signle signals, ie. dut.register_file.conf[7:0]
  • in gatelevel the registers are split to single flip-flops, ie. dut.register_file.conf_reg_7, dut.register_file.conf_reg_6 … dut.register_file.conf_reg_0

I would like to avoid having two separate registers descriptions files (.cvs) for RTL and gatelevel verification, as it could be error prone (possibility of mismatch between two descriptions). I noticed that add_hdl_path in reg_uvm has the kind argument. Thus:

  1. Is it possible to define in a single register description file (.cvs) for RUVM4.6 two kinds of backdoor paths?
  2. How to specify in the description file (.cvs) for RUVM4.6 a backdoor path combined of many single registers (according to UVM 1.1d documentation, reg_uvm.add_hdl_path could process a path defined as:

reg_h.add_hdl_path('{ '{"conf_reg_7", 7, 1},
'{"conf_reg_6", 6, 1},
'{"conf_reg_5", 5, 1},
'{"conf_reg_4", 4, 1},
'{"conf_reg_3", 3, 1},
'{"conf_reg_2", 2, 1},
'{"conf_reg_1", 1, 1},
'{"conf_reg_0", 0, 1} },
"GATELEVEL" );