If we have 3 to 4 module in RTL, of that how should we decide which one is the design under test(DUT)?
In reply to Muthamizh:
Look for rtl_top file or file where all modules are instantiated in the rtl directory. Instantiate that file in the tb_top module.
Dont think this question or answer makes sense. No offense to anybody.
DUT is what you WANT to verify. This is decided by what your verification boundaries are. For a design, verification boundaries are decided by how many logical splits of the design one wants.
The designer would usually know what is the TOP of the DUT is if the RTL is a mash of different modules in the same file. One could verify different modules of this RTL separately or all together. Logically split the design into manageable parts and draw your verification boundaries.
In reply to kernalmode1:
I also know that I could verify each module of RTL separately. I wanted to know, how to know the top module of the design, thats all.
Thank you
TOP of a design is usually known to the designer. It is not necessary that it be named “rtl_top”. One usually asks the code writer or analyze to find out what module comes out as the TOP. Without seeing the relevant code, it would be highly illogical for a third person to answer what the TOP of a DUT would be.