Round robin arbitration logic for analysis ports

UVM
1

I have to verify RTL with 4 ports.
I have 4 analysis ports and corresponding imports.
Each port has its own write method.
write method, creates address and data entry in array.
If one port is selected at a time then this logic works fine.

Now if one or many ports are sending input to RTL at same time, then i need round robin arbitration logic, with port0 having highest priority.
ex: if port0, port1, port2 and port3 are initiating traffic at same time, then first address and data entry should be created from port0 then from port1 then from port2 and then from port3.

can anyone please suggest how do i implement this logic

2

In reply to ssp.3010@gmail.com:

To understand correctly: You are sending data through an analysis port to yout RTL design. Is this really the case. I’d expect your RTL requires acertain protocol for processing data.
If you have more than 1 analysisi port with different write functions you have to use the uvm_analsis_imp_decl macro which allows to add to yout write function and the analysisi port a suffix.