Role of 'parent' in register write/read

UVM
1

Hi,

The argument parent of register write/read tasks is null by default.
Sometimes I see that parent is being set to this. And sometimes it’s left null.
For convenience, UVM also provides methods such as write_reg or read_reg which implicitly sets parent to this.

But the role or the meaning of this parent in register write/read is not clear to me.
Can anyone help me understand it?

task uvm_reg::write(output uvm_status_e      status,
                    input  uvm_reg_data_t    value,
                    input  uvm_path_e        path = UVM_DEFAULT_PATH,
                    input  uvm_reg_map       map = null,
                    input  uvm_sequence_base parent = null,
                    input  int               prior = -1,
                    input  uvm_object        extension = null,
                    input  string            fname = "",
                    input  int               lineno = 0);

Best regards,
Jung Ik Moon