Reusing register init sequence from block to subsystem/chip level

UVM
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1

Hi,

How to re-use the register sequence from Block(IP) in Subsystem/Chip level.

Thanks
Saravanan

2

In reply to saravanan_kpk:

If you still have access to the bus on bothh levels you can reuse the register sequences as they are.

3

In reply to chr_sue:

Hi Chr_sue,

When we use same register sequences from block to subssystem/chip. How the address conversion is handled.

  1. At block level we have only offset.
  2. At subsystem we have BLOCK_BASE_ADDR + offset
  3. AT chip we have SUB_SYS_BASE_ADDR + BLOCK_BASE_ADDR + offset
4

In reply to saravanan_kpk:

You were asking for reusing register sequences and not the register model integration and setup.
Looking to the model integration you are completely right.

5

Hello, Saravanan.
For instance, your RAL(register abstraction layer) sequence should consume only uvm_reg_map. Through gotten map you could receive all regs. Register map has all information how access for any register should happen (via frontdoor or via reg_adapter). This information in map appeared when add_reg() method was called with some protocol dependent frontdoor or when set_sequencer() method was called with protocol dependent sequencer and adapter. But in reusable RAL sequence, you could operate only protocol independent abstract information: some map, some registers, read()/write() methods calls.
Best regards, Maksim.

6

In reply to chr_sue:

Hi,

Do UVM RAL itself takes care of Address computation by itself depending on IP/SUB_SYSTEM/SOC ?

7

In reply to saravanan_kpk:

If the register do not change and you do not add additional register in a higher level all information from blcklevel can be reused.