Reusing bit blash sequence for pipe lined protocol like AHB

Hi,

Is there is any way to implement uvm_reg_bit_blash sequence for protocols like AHB/AXI. where the driver has to give item_done to sequence to fetch the next request without waiting for response.

In reply to saravanan_kpk:

The ability to pipeline register reads and writes is a function of the register adapter.

Normally, register writes are pipelined, but reads are atomic. Therefore, the register adapter will create the appropriate atomic operations for each register transaction. This may not be true in all cases, so you may see different behavior.