Reuse the design task inside the class

UVM
,
1

Hi All,

I have an one doubt. I have a task inside the design top module. How can I reuse it inside the class ex:- in Driver (in UVM test bench)? Can I use using $root?

Thanks
Kapil

2

In reply to kapil khare:
See OVM wrapper for Verilog Bfms?? | Verification Academy

It is a very old thread - look towards the end for updated examples.