Reset methodology in UVM environment

Hi UVM forum,
I need to implement in my UVM environment a reset methodology.
It means that reset (actually few of them but lets start with one) can assert at any time in the simulation.
not necessarily in reset_phase but mainly in run_phase.
Is there a methodology to clean up all components (scb, agents), clean sequencers queues, kill sequences and start all over again?

In reply to shimonc:

Could you please explain what kind of reset do you have. Is it a simple asynchronous/synchronous reset or do you have a reset procedure.
You’ll have a clean behavior only if you do not kill sequences. and you do not need the reset_phase. You can do all these things form the run_phase executing a reset sequence. You might clean-up storage elements like uvm_analysis_fifo. But this depends on your implementation details. All what is in these fifos has been stimulated and it might be useful to process/compare these seq_items.

In reply to chr_sue:

Hi, my chip is big SoC.
It has interfaces to analog component (ADC, DAC, comparators etc)
It has interfaces to CPU serial communication protocol.
it has interfaces dedicated to external IC that talk with him in non standard protocol.
and he also have RESET PIN (async)
now the chip is working for a allot of time after power up (TLM’s run crazy).
After 1 year of operation the user decides to assert the reset.
all the sequences might in the middle of transaction.
sequencers might have big queue in there FIFO.
Scoreboards might be in the middle of PASS/FAIL evaluation
etc.
If I won’t take the correct actions I will get hundreds of UVM_ERROR

In reply to shimonc:

I see you have very different interfaces. The key question is what happens when you are stopping the execution of an interface protocol in the middle of the protocol schedule.
Sequencers do not have big FIFOs. The default FIFO depth is 1 and this is useful, because the generation of a seq_item does not consume time.
Important is what shall happen with the analysis FIFOs.

In reply to chr_sue:

regarding your question “what happens when you are stopping the execution of an interface protocol in the middle of the protocol schedule”.
obviously the RTL is on reset state, all FSM’s start from IDLE state, communication transaction are thrown away.
UVM is in the middle of evaluating results.
I thought that there is a working methodology on this issue.
Following is a quote in a paper I read on this subject

"The Accellera UVM phasing sub-committee has been trying to resolve how to handle
resets using the phases

  • the solution is still incomplete after a long time
  • Existing limitations will likely require changes to UVM library"

In the mean time I’ll try to develop my own solution

In reply to shimonc:

The quote you mentioned points to the so called sub-phases of the run_phase, i.e. reset_phase, config_phase etc.
In my knowledge this is ina very poor status and it creates more confusion as clarity.
I have not seen any really good example for using these sub-phases.
In the run_phase you can run a reset-sequence, a configuration sequence etc.
This is what I’d recommend also for your work. Run a reset-sequence in any place you believe it should be. You can initiate such a sequence at a random place.
I’d be very careful killing sequences.