In reply to chr_sue:
regarding your question "what happens when you are stopping the execution of an interface protocol in the middle of the protocol schedule".
obviously the RTL is on reset state, all FSM's start from IDLE state, communication transaction are thrown away.
UVM is in the middle of evaluating results.
I thought that there is a working methodology on this issue.
Following is a quote in a paper I read on this subject
"The Accellera UVM phasing sub-committee has been trying to resolve how to handle
resets using the phases
- the solution is still incomplete after a long time
- Existing limitations will likely require changes to UVM library"
In the mean time I'll try to develop my own solution