Hey all,
I’m trying to apply reset at any randomized time point in simulation, As initial block at tb top deasseted only once. I used to create a new interface to assert or de-assert reset in the middle of a functionnal sequence. But i wonder if there s other method than this one?
I read in this forum that i can add reset in seq item then randomized but i’m not sure of that approch cuz in the driver i would make seq_item.reset which i never saw in a uvm code, I only find vif.reset
In reply to abdelaali_21:
Create a separate agent/driver/interface to handle reset.
See How to deal with initial reset of DUT? Use of Reset phase or Sequence | Verification Academy
In reply to dave_59:
Create a separate agent/driver/interface to handle reset.
Hey Dave, thanks for replying, i read about virtual sequence and it was enlightning. However, I want to create an agent to control reset signal, in which the driver assert or deassert reset, but i have this question :
I only created driver with no get_next_item, i didn’t used sequencer cuz i don’t know what to pass to driver as a seq item & I wonder how this reset sequence will be started by virtual sequence if there’s no sequencer associated.
In reply to abdelaali_21:
Your reset sequence item can be as simple as a bit you was to set the reset pin to, or you can make it a little more intelligent by specifying the amount of time or cycles you want reset to be applied.
A reset agent needs a sequencer to send items to the driver. To create a balance sequence hierarchy, you would need to create reset sequence that sends the sequence_item to the driver. But there is nothing wrong with having your top-level sequence sending sequence_items directly to the driver through the reset sequencer.