Dear All,
I’m trying to understand the below code. In especially,
Where exactly ‘req’ comes from?
module test_top;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "uart_frame.sv"
class uart_sequencer extends uvm_sequencer #(uart_frame);
`uvm_component_utils(uart_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : uart_sequencer
class uart_tx_driver extends uvm_driver #(uart_frame); //lab2_note3
int frames_sent;
`uvm_component_utils(uart_tx_driver) //lab2_note4
task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
frames_sent++;
send_to_dut(req);
seq_item_port.item_done();
end
endtask : run_phase
task send_to_dut(uart_frame frame);
repeat (frame.delay)
endtask : send_to_dut
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : uart_tx_driver
`include "uart_seq_lib.sv"
uart_sequencer sequencer;
uart_tx_driver driver;
initial begin
uvm_config_wrapper::set(null, "sequencer.run_phase", "default_sequence",
uart_nested_seq::type_id::get());
sequencer = new("sequencer", null);
driver = new("driver", null);
driver.seq_item_port.connect(sequencer.seq_item_export);
run_test();
end
endmodule
class uart_base_seq extends uvm_sequence #(uart_frame);
`uvm_object_utils(uart_base_seq)
function new(string name="uart_base_seq");
super.new(name);
endfunction
task pre_body();
starting_phase.raise_objection(this, get_type_name());
`uvm_info(get_type_name(), "raise objection", UVM_MEDIUM)
uvm_test_done.set_drain_time(this, 200ns);
endtask : pre_body
task post_body();
starting_phase.drop_objection(this, get_type_name());
`uvm_info(get_type_name(), "drop objection", UVM_MEDIUM)
endtask : post_body
endclass : uart_base_seq
class uart_transmit_seq extends uart_base_seq;
`uvm_object_utils(uart_transmit_seq)
rand int unsigned NumOfTx;
function new(string name="uart_transmit_seq");
super.new(name);
endfunction
constraint NumOfTx_ct { NumOfTx >0; NumOfTx <= 10; }
virtual task body();
uvm_report_info("uart_transmit_seq", $psprintf("Executing %0d times", NumOfTx), UVM_LOW);
for (int i = 0; i < NumOfTx; i++) begin
`uvm_do(req)
end
endtask: body
endclass: uart_transmit_seq
class uart_nested_seq extends uart_base_seq;
uart_transmit_seq transmit_seq;
`uvm_object_utils(uart_nested_seq)
virtual task body();
`uvm_do_with(transmit_seq, {NumOfTx==3;})
endtask: body
endclass: uart_nested_seq
From example above, WE can see the ‘req’ keyword used in a sequence class without any declaration.
So I want to know that can we use ‘req’ keyword without something relative declaration? does it reservation keyword for UVM?