Hi,
I want to access (or check and report an uvm_error) during uvm report_phase.
This need to be done from within system verilog interface module.
Using ‘final’ instead of report_phase doesn’t go well with the current verification flow.
Is there a simple way to achieve this.
PR
In reply to prniar:
As you might know the UVM phasing is related to the classes and not to modules and interfaces.
I would be interested why you want to use the report phase out of an interface.
In reply to chr_sue:
TB has few stand alone interfaces which does checking, just want to ensure certain level of checks happened before simulation ends. Would like it to happen inn interface so that all is contained within the interface as opposed probing/managing it externally.
Doing that in report phase also works well with the overall dv regressions scripts.
In reply to prniar:
The report_phase is a UVM phase which will be executed after the run_phase, i.e. after the simulation run itself has ended.
I understand from your explanation you want to implement some uvm_info to indicate your checks were successful or some uvm_error to show something went wrong. Right?
In reply to prniar:
The simple way is constructing a uvm_component inside your module or interface.
module something;
class my_check extends uvm_pkg::uvm_component;
...
function void report_phase(uvm_phase phase);
// your code here
endfunction
endclass
my_check h=new("my_check",null);
...
endmodule
Construction of the class will enable the report_phase to get executed.
Phase mechanism only for classes (specially for Components in UVM testbench architecture),
while interface and module are static entity we can’t use phase mechanism .
In reply to dave_59:
In reply to prniar:
The simple way is constructing a uvm_component inside your module or interface.
module something;
class my_check extends uvm_pkg::uvm_component;
...
function void report_phase(uvm_phase phase);
// your code here
endfunction
endclass
my_check h=new("my_check",null);
...
endmodule
Construction of the class will enable the report_phase to get executed.
dave sir,
class my_check extends uvm_pkg::uvm_component;
what is meaning of this extention ,
normally i am using :- class shubham extends uvm_component;
please tell me what is importance of uvm_pkg here
In reply to uvm_verification:
It is an explicit package reference that you can do instead of the wildcard import of the uvm_pkg::*.
See section 26.3 Referencing data in packages in the 1800-2017 LRM.
Thanks dave Sir.