Regmodel sequencer and adapter

UVM
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1

Hi all!
I hope you’re all doing great !
I’m trying to implement a regmodel in my uvm tb, I created it and i set the sequncer where it reg sequence should run with adapter.
in the env :


// connect phase
model.default_map.set_sequencer(vseq.a_seqr,adapter)

in the adapter, I transalte reg seq item to protocol seq item


reg2bus:
populate protocol seq item 
return protocol item;

When i launch a reg.read I get the following error :
UVM_FATAL : attempting to start a sequence using start_item() from sequence ‘default_parent_seq’. Use seq.start() instead

2

In reply to abdelaali_21:

Hey all!
I finnaly solved the issue. Well, The ral adapter wans’t converting from to the right bus items, and, when i had the right adapter, I made sure that s connected the sequencer then in the run phase of the test I ran the reg sequence on a null sequencer.
Hope this helps