The UVM User Guide provides an integration model for the uvm_reg_sequence that I find interesting: running on a layered register sequencer.
Browsing the Web, except for the User Guide itself, I couldn’t find a lot of resources discussing the topic and I was wondering why.
The proposed model exposes the internal “virtual sequencer” reg_seqr, and passes it to the regmodel.default_map, but it doesn’t provide the adapter in the set_sequencer method 'cause the translator sequence will do it by itself, instead of having the register model translating the items. Here below is the snippet from the Guide.
typedef uvm_reg_sequence #(uvm_sequence #(apb_rw)) reg2apb_seq_t;
// ...
uvm_sequencer#(uvm_reg_item) reg_seqr;
reg2apb_seq_t reg2apb_seq;
virtual function void connect_phase(uvm_phase phase);
if (regmodel.get_parent() == null)begin
regmodel.default_map.set_sequencer(reg_seqr,null);
reg2apb_seq = reg2apb_seq_t::type_id::create(“reg2apb_seq”,,get_full_name());
reg2apb_seq.reg_seqr = reg_seqr;
reg2apb_seq.adapter =reg2apb_adapter::type_id::create(“reg2apb”,,get_full_name());
regmodel.set_auto_predict(1);
end
endfunction: connect_phase
virtual task run();
reg2apb_seq.start(apb.sequencer);
endtask
I believe the task run() is actually a run_phase(uvm_phase phase), since we want to make sure the translator sequence runs on the bus adapter and is ready to translate the uvm_reg_items as they come.
The register sequence then is started on the register sequencer as you would normally run a virtual sequence on a virtual sequencer:
virtual function void run_phase(uvm_phase phase);
my_reg_sequence seq = my_reg_sequence::type_id::create(“seq”,this);
seq.start(env.reg_seqr);
endfunction
Any comment on why this method is not much discussed or used? Any drawbacks in using this model?