Front-door access is the "natural" way that the RTL accesses the registers, using a bus with a specific protocol defined for the bus.
Usually as a verification engineer there is less work to be done in the test-bench in order to support it.
Back-door access needs additional support to be added to the TB:
1. You need to supply HDL_PATH of the registers, and keep in mind to make the path re-useable for higher levels.
2. It can be tedious if you have un-conventional registers, for example: indirect registers.
So why Back-door access is needed if it adds additional work?
1. It saves precious simulation time.
Imagine hundreds or even few thousands of registers to be written in order to configure
the initial DUT state of the block/IP/Full-Chip. It might consume 99% of your
simulation time, before actual traffic starts running and sometimes lasts for few hours (or even days, depends on complexity of the product).
Debug iterations will be extremally long, schedule of project will be bad. Daily job will be frustrating.
2. Some kind of registers cannot be written using front-door access type... So you need to load values into them using back-door access as chr_sue mentioned. Same thing is right for loading memories.