Register model for a register that can be either RO or WO based on another register setting

I am using UVM1.2.

I am creating a register model for a register that can be either read only or write only based on another register setting (lets assume the controlling register is mode, and the register in question is data).

Can you guide me on how to do that or do you have an example for this case?

Victor,

In reply to victorh:

I am using UVM1.2.
I am creating a register model for a register that can be either read only or write only based on another register setting (lets assume the controlling register is mode, and the register in question is data).
Can you guide me on how to do that or do you have an example for this case?
Victor,

you can use register callbacks in this case.

In reply to Alokpati:

Can you provide an example for that? I cannot see similar examples available online?
I can only see an example that changes the value of a RO register using predict() function but not the access permissions.

Is there a way to change access permissions during run time?