I have UVM-based testbench with, say, an APB bus.
Both C code and internal verilog sequences are used to initialise DUT via this bus. I use UVM register model for this purpose, as adviced in this video:
At first initialzation with C code happens, then verilog code randomly reprograms some of the registers.
It seems to me, that eventually C code will not know, what exactly is the state of the registers, and the only way for C code to find it out now, is to make a full read of all the registers from DUT, which is not efficient.
What i would like to have, is for C code to get access to the whole memory with one request and without any activity happening on DUT inputs. So basically i want to access the register model itself from C code. Could anyone please tell me, what is the best way to do it? Have anyone ever encountered such a problem at all?