Hi UVM forum,
I have a problem where the adapter method bus2reg is been called twice.
in my sequence I have a simple register read.
m_model_reg.m_vmain_meas1.read(status,rdata)
My intention is that only the monitor which collect transactions from the bus will update the reg model.
But after many hours of debugging I found out that also the driver update the reg model.
I found that by changing req before item_done
// driver run phase
seq_item_port.get_next_item(reg);
drive(req);
// Change req data
req.data=16'AAAA;
seq_item_port.item_done();
and printing the sequence item in the adapter method bus2reg.
and verify that the artificial data that I wrote to req is been printed when bus2reg is been called.
How can I set the reg model to be updated only if the monitor sends transactions via is analysis port,
and not by sequencer-driver-sequencer handshake?