Register model

Hi UVM forum,
I have a problem where the adapter method bus2reg is been called twice.
in my sequence I have a simple register read.


m_model_reg.m_vmain_meas1.read(status,rdata)

My intention is that only the monitor which collect transactions from the bus will update the reg model.
But after many hours of debugging I found out that also the driver update the reg model.

I found that by changing req before item_done


// driver run phase
seq_item_port.get_next_item(reg);
drive(req);
// Change req data
req.data=16'AAAA;
seq_item_port.item_done();

and printing the sequence item in the adapter method bus2reg.
and verify that the artificial data that I wrote to req is been printed when bus2reg is been called.

How can I set the reg model to be updated only if the monitor sends transactions via is analysis port,
and not by sequencer-driver-sequencer handshake?

Unfortunately, this has been asked before and no solution was found, or at least not reported.

https://verificationacademy.com/forums/uvm/uvmregadapter-bus2reg-called-twice-predictor

In reply to shimonc:

Shimonc, your understanding is wrong. Executing a read from a sequence is reading from the register model in your testbench and it is starting a bus cycle on the physical interface using the sequencer/driver of the corresponding agent. To support this functionality you have bus2reg and reg2bus functions in your register adapter. The monitor is completely passive. It is only observing your data, i.e. it should observe the read cycle on the virtual interface and see also the correct read value.

In reply to chr_sue:
Thanks, I got it.