Register Active Monitoring in UVM

UVM
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I have a register that gets the value of an FSM state in the DUT. I would like to keep this register updated with the latest FSM state value whenever there is a change in the DUT. To implement this i was reading about active monitoring through uvm backdoor. I want to monitor the DUT all the time, and if the state of FSM changed, register model will update automatically and then i can read the register model to know the present state of the FSM. Can someone help me out with an implementation of active monitoring or any other material regarding its implementation other than the Accelera material.

Thanks in advance.

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In reply to saikiran1825:

See How to access DUT signal from agent component | Verification Academy

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In reply to dave_59:

Hi Dave,

Thanks for the reply, but i would like to read the register in the register model to get the latest value of the fsm in the DUT rather than reading a signal from DUT. That’s why i was thinking about the active monitoring. Can you help me out with implementation of active monitoring in the register model using backdoor access.

Thanks.