Register Access by 3 interfaces

UVM
,
1

Hi,
I have a register bank, which can be accessed by 3 different interfaces (different protocols). How can I implement this using RAL.

a) Should I have 3 instances of the reg model and connect them to the three different sequencers ?
b) If I write through one interface - say reg1 through IF1, how can I make sure the reg1 values will get reflected for the other interface also (since it is the same set of registers)

Thanks in advance.

2

In reply to umagraman:

Hi,

You can take multiple register map instances and configure them for a number of required interfaces. you can refer the following document for multiple register map ([Click here…])(Section : RAL register map and adapter)

Also, find answers inline.

a) Should I have 3 instances of the reg model and connect them to the three different sequencers?

Answer:- Yes, For each bus, a sequencer is required to be configured.

b) If I write through one interface - say reg1 through IF1, how can I make sure the reg1 values will get reflected for the other interface also (since it is the same set of registers)

Answer:- Ideally, this should be your test criteria as the register is the same but access interface is different. You can write register with one register map and read_compare with other all register maps. (There is an inbuilt register sequence (uvm_reg_shared_access_seq) which you can use)

Regards,
Mitesh Patel

3

In reply to mitesh.patel:

Thank you Mitesh.

4

Hi Mitesh

How will the write method distinguish which interface it has to use among the 3 - cause I am not passing any details on that

  1. reg1.write(value) // Write thru IF1
  2. reg2.write(value) // write thru IF2
  3. reg3.write(value) // writhe thru IF3

Regards
Uma

5

In reply to umagraman:

The map associated with a register object dictates which interface it uses. If you have a register associated with multiple maps, you must provide the map detail when calling write(). There is no default map.

6

In reply to umagraman:

When you are dealing with multiple bus interfaces, then each interface must be allocated for separate register map. from the write method, the user has to pass the map handle ( which will drive to an allocated interface).

7

Thanks Dave.
In my case, the 2 interfaces dont have seperate Base Address. We differentiate them by writing a particular value into interface_no register. Eg., If IF1 wants to write the DUT registers, it writes the register address in a predefined address - say 1A. If IF2 wants to write the same regsiter, it writes the register address into -1B.

So,when I create the map for IF1 and IF2, BA and offset will be same

So, even if I pass the register map for IF1,IF2 during calls to write or read, will it be able to differentiate?

Or Should I pass any more options.

8

Thank you Mitesh.

In my case, the 2 interfaces dont have seperate Base Address. We differentiate them by writing a particular value into interface_no register. Eg., If IF1 wants to write the DUT registers, it writes the register address in a predefined address - say 1A. If IF2 wants to write the same regsiter, it writes the register address into -1B.

So,when I create the map for IF1 and IF2, BA and offset will be same

So, even if I pass the register map for IF1,IF2 during calls to write or read, will it be able to differentiate?