Register Abstraction Layer

Hi UVM forum,
I have a question about RAL.
In a previous questions I already refer to this subject, but I didn’t ask the question correctly.

The register model is been update by the function bus2reg which is one of two uvm_reg_adapter methods.
The bus2reg method is been called by two sources.

source number 1 is the seq_item_port.item_done() which is activated usually in the driver (sequencer-driver handshake).
source number 2 is the bus monitor which is connected to the RAL via the commands


   predictor.map=register_model.default_map;
   agent.monitor.ap.connect(predictor.bus_in);

One could ask why do we need both sources?
The answer is that we want to catch transactions in the bus that didn’t originate from communication interface.

In my application all the registers are been accessed by communication interface.
However the fact that both the driver and the monitor updated the RAL causes me some problems.
I over come these problem by adding more code to the bus2reg method.
The code understands what is the source of the transaction and deal with it in 2 different ways depending on the transaction source.
My question is. Do we have in UVM an option to prevent the seq_item_port.item_done() from calling the adapter bus2reg method?