Reg_field.configure(..volatile());

UVM
1

In the RAL model reg_field.configure method, when the argument {.volatile(0)} has to be setted to zero and when it has to be setted {.volatile(1)} to one , on what register specification this has to be decided?

function void configure( uvm_reg  	parent,
	           int  	unsigned  	size,
	           int  	unsigned  	lsb_pos,
		   string  	access,
		   bit  	volatile,
		   uvm_reg_data_t  	reset,
		   bit  	has_reset,
		   bit  	is_rand,
		   bit  	individually_accessible 	);
2

In reply to vijay kumar gannoju:

The UVM Reg model considers a RW register “volatile” if it can change its value through some other mechanism not observable through a monitored interface. This means if you write to it, you cannot predict its value from a subsequent read.

3

In reply to dave_59:

could you pease elaborate it…

4

In reply to dave_59:

Hi Dave ,

Lets say we have a register with SW access as “RO” and HW access as “RW/WO” .

So if we were to write into it ( obviously it wouldn’t be reflected in register ) , so when we read it back ,
[A] Should it ( mirrored value ) would expect the default value to be read back ?

[B] But since HW is free to write into it , would we get a mirrored value mismatch ?
Even using volatile bit for the fields doesn’t resolve the issue

So how should we solve this issue ?
5

In reply to TC_2017:

There is no such thing as SW versus HW access—it’s all hardware.

This might answer your question.

6

In reply to dave_59:

Hi Dave ,

Is the volatile bit set , sufficient for no mismatch error ( between mirrored value and value read from register ) ?

Although I have set volatile argument for all uvm_reg_fields within a register ( with access as “RW” ) , I still see a mismatch error on doing a random write and read . The value read is different than the random value written , hence the mismatch .

7

In reply to dave_59:

Hi Dave,
Can you please elaborate the above explanation. Unable to understand clearly