I’ve started to educate myself in IP verification using SystemVerilog and UVM. However one thing that confuses me is the concept of Interfaces. I understand how to use them, their functionality and how they are helpful. However, as far as I know, if I write a module in plain Verilog (let’s say a simple ALU) which I then need to verify, the DUT will NOT have an interface, but rather the classical port delclaration (as it is meant to be synthesizeable). As far as I’ve been able to find, this means that the interface that I create will still need to be connected port by port to the module.
Doesn’t this beat the purpose of the interface?. It’s all fine when the DUT is written in SystemVerilog, but not when it is written in Verilog, which to my understanding, is the most common case.
I’d appreciate an explanation (and a little code example, if possible).
You are correct that an interface needs to be connected port by port to a legacy Verilog module or VHDL entity. And you are also correct in your observation that Verilog is still more prevalent for design than SystemVerilog. But that is rapidly changing as most synthesis tools have added support. For FPGA designs, Verilog has dropped to 50%. But for RTL verification, SystemVerilog is now the predominate language.
The there are two reasons people use interfaces in verification even when cponnecting to a Verilog DUT. It is a handy construct to put all the behaviors associated with in physical interface, like pull-ups/pull-downs, and protocol checkers in the form of assertions. It also is a way of removing physical and hierarchical dependancies of your DUT, making your testbench more reusable. As you move from block-level to system-level testbenches, the SystemVerilog interfaces makes it easier to encapsulate the physical interface and you can use the bind statement insert an interface connection inside your design. See my DVCon paper The Missing Link: The Testbench to DUT Connection
From a technical standpoint SV interfaces are synthesizable and hence any new RTL block can/should use them. With legacy code, yes you would need to connect them port by port. Isn’t that true for any new (relatively) feature?
Hi. Thanks for the reply’s. I am not questioning the validity of interfaces, I merely wanted to understand them. Your reply’s have been most helpful. Thank you very much.