Regarding usage of $sformatf with assign statement in generate block

UVM
, , ,
1 
generate
for(genvar idx=0; idx<16; idx++)begin//{
  assign $sformatf("p%0d_mfr_mdfiss_axiclk_aclk",idx) = mfr_axi_if.master_if[idx].aclk;   //assignment-1
  assign mfr_axi_if.master_if[idx].arready = $sformatf("p%0d_mfr_mdfiss_data_axi_sport_arready",idx);  //assignment-2
end
endgenerate

I’m getting below error :
Error-[SE] Syntax error
Following verilog source has syntax error :
“/nfs/site/disks/alr_mfr_001/csg/mdfiss_Sept8/src/val/tb_top/mdfiss_tb_top.sv”,
61: token is ‘$sformatf’
assign $sformatf(“p%0d_mfr_mdfiss_axiclk_aclk”,idx) = mfr_axi_if.master_if[idx].aclk ;

what’s wrong with these two assignments?
Is it not permitted to use $sformatf to use like this ?
If there is way, please let me know how to use…

Quick response will be really helpful.

Thanks in advance.
Chandrashekar

2

In reply to chandrashekarsg:

SystemVerilog is a compiled language (like C); you cannot build hierarchical references to signal name identifiers from strings. I suggest you use your text editor to replicate the lines of code.

There are other tool specific mechanisms to access signal names by string, but not very efficient. Check with your vendor.

3

In reply to dave_59:

Thank you so much for your quick response Dave…
I have got a reference where you have told the below in one of the past post. I felt bit of contradiction. So asking to clear my doubt.

If you want to keep the continuous assignment, then you need to use $sformatf
generate
for (ganvar num = 0; num < 12; num++) begin
assign hello_if.fruit[num] = $sformatf(“`HELLO.fruit_num%0d”, num);
end
endgenerate

https://verificationacademy.com/forums/systemverilog/it-not-allowed-use-sformat-inside-generate-statement

Thanks,
Chandrashekar

4

In reply to chandrashekarsg:

That example was a generate-for loop being used to construct a string. It was not clear what they intended to do with it.

5

Hi Chandrashekar,

If your requirement is just assigning a valueto a variable in anyway, even the uvm_hdl_force works.


generate
  for(genvar idx=0; idx<16; idx++)begin
    uvm_hdl_force($sformatf("p%0d_mfr_mdfiss_axiclk_aclk",idx),mfr_axi_if.master_if[idx].aclk); 
  end
endgenerate

-mpattaje