Regarding TLM Port width

Hi everyone,

Can anyone help me, “How to override the width of the TLM port”??

My scenario is like, I have a driver which is having a dynamic array of type “bit [39:0]frame”, I am framing an array by getting each packet from the transaction class which is of type “bit [39:0]data” for every iteration in my driver, So now my intention is to put the “frame” into an “uvm_blocking_put_port” and thereby getting the packet into an another component using “uvm_blocking_put_imp”. Here the main issue is that “put_port” is always carrying of type int only, but according to my scenario it should be capable of carrying 40-bit instead of 32-bit.

Thanks in advance,
Kishore Malla

In reply to KISHORE MALLA:

A TLM port/export does not have a width. It is parameterized for an object.
See the UVM Cookbook UVM | Verification Academy for more details.

A TLM port/export does not have a width. It is parameterized for an object.
See the UVM Cookbook UVM | Verification Academy for more details.[/quote]

Thank you chr_sue, I got my issue. Thanks for the suggestion.