Regarding timing constraint for input

UVM
1

Hi

I want to drive inputs we(write enable), cpu_addr and cpu_data for oly one clock cycle i mean on the same clock and for 1 clock cycle i am not able to do that.

Can anyone suggest me using wt we can drive 3 signals on same clock & for 1 clock cycle.

2

In reply to Swathi BN:

What have you created so far? Do you drive the signals in the interface or the driver class?

3

In reply to chrisspear:

Thank you for your response i got the solution.

I have created in driver and its working now.