may i know what is master and slave ,and how exactly master and slave communicates with each other,test flow
if any one have AHB TESTBENCH ARCHITECTURE please share me…
In reply to rc227:
In general a master component initiates commands, and a slave component responds to commands. Communication is protocol dependent.
A good tutorial about dealing with master/slaves in a UVM testbench is here:
An AHB example: https://www.edaplayground.com/x/ShDj