Regarding dual port ram verification

Hi,
Can anybody tell me why i able to get output(data_out) in my code.Please help me…
I am giving the link of the code- UVM-1(3) - EDA Playground

In reply to Raneesh Kumar:

Are you sure your code is accessible for everybody? I do not see anything …

In reply to chr_sue:

Thank you so much for replying Sir…

Sir my code link is- UVM-1(3) - EDA Playground

I am not able to get my output data_out…help me sir

In reply to Raneesh Kumar:

Your s_monitor content is wrong. You have to synchromite on the clock edge and not on the read. Additionally look to your design for read it needs 2 clock edges.

In reply to Raneesh Kumar:

  1. you are randomize the both write address and read address.if both write address and read address are matched then at the next clock cycle you get the data_out.(driving the stimulus with fixed address in one test case and check the answers and other ways use temporary registers to cover all the memory locations)

2.and in interface slave driver clocking block your not included the data_out port.

In reply to chr_sue:

ok thank you sir.

In reply to mada saimanasa:

ok thanks…