Regarding connecting Interface to RTL and RTL to Interface

UVM
,
1

I have simple interface and a RTL block. I have 2 instances of same interface and 2 instances of same RTL. I would like to connect it in this way. So basically i want to drive interface 1 which is fed to DUT1 and DUT1’s signals are fed to DUT 2 and then DUT2 is connected to Interface 2. what changes i need to make it at the top level?
Interface 1 → DUT1 → DUT2 → Interface 2



module top;
  import uvm_pkg::*;
  import my_testbench_pkg::*;
  
  // Instantiate the interface
  dut_if dut_if1();
  
  dut_if dut_if2();
  
  // Instantiate the DUT and connect it to the interface
  dut dut1(.dif(dut_if1));
  
  dut dut2(.dif(dut_if2?));
  
 
  
  
  // Clock generator
   // Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, top);
  end
  
  initial begin
    dut_if1.clock = 0;
    forever #5 dut_if1.clock = ~dut_if1.clock;
    
  end
  
  
  initial begin
    // Place the interface into the UVM configuration database
    uvm_config_db#(virtual dut_if)::set(null, "*", "dut_vif1", dut_if1);
    
    
    // Start the test1
    run_test("my_test");
  end
2

In reply to rag123:

I assume the reason you created two instances of the same interface is because you need to cross connect the outputs of one interface signals to the inputs of the other interface instance. The only way to do that is with a set of continuous assignments or some other RTL code for each signal in the interface

assign dut_if2.clock = dut_if1.clock;
assign dut_if2.A = dut_if1.B;
assign dut_if1.A = dut_if2.B;