class sys_reg extends uvm_reg;
`uvm_object_utils(sys_reg)
// uvm_reg_field bypass_en; //bypass mode enable
uvm_reg_field reset; // reset mem
uvm_reg_field cke_control; //cke control, sdram
function new(string name = "sys_reg");
super.new(name,3,build_coverage(UVM_NO_COVERAGE));
endfunction
virtual function void build();
// bypass_en = uvm_reg_field::type_id::create("bypass_en");
this.reset = uvm_reg_field::type_id::create("reset");
this.cke_control = uvm_reg_field::type_id::create("cke_control");
// bypass_en.configure(this,0,0,"RW",1,1'h0,1,1,0);
reset.configure(this, 1, 1, "RW", 1, 1'h0, 1, 1, 0);
cke_control.configure(this,2,0, "RW", 1, 2'h0, 1, 1, 0);
endfunction
endclass
class bypass_reg extends uvm_reg;
`uvm_object_utils(bypass_reg)
// uvm_reg_field cs_control;
uvm_reg_field we_control;
uvm_reg_field cas_control;
uvm_reg_field ras_control;
uvm_reg_field address;
uvm_reg_field bank_add;
function new(string name = "bypass_reg");
super.new(name,21,build_coverage(UVM_NO_COVERAGE)); //26+1+1+1+64+64
endfunction
virtual function void build();
// cs_control = uvm_reg_field::type_id::create(“cs_control”);
we_control = uvm_reg_field::type_id::create(“we_control”);
cas_control = uvm_reg_field::type_id::create(“cas_control”);
ras_control = uvm_reg_field::type_id::create(“ras_control”);
address = uvm_reg_field::type_id::create(“address”);
bank_add = uvm_reg_field::type_id::create(“bank_add”);
//cs_control.configure(this,0,0,"WO",1,1'h0,1,1,0);
we_control.configure(this,1,0,"WO",1,1'h0,1,1,0);
cas_control.configure(this,2,0,"WO",1,2'h0,1,1,0);
ras_control.configure(this,3,0, "WO",1,3'h0,1,1,0);
address.configure(this,13,4,"RW",1,13'h0,1,1,0);
bank_add.configure(this,2,17,"RW",1,2'h0,1,1,0);
endfunction
endclass
class time_reg extends uvm_reg;
`uvm_object_utils(time_reg)
uvm_reg_field t_rp; //clk_precharge
uvm_reg_field t_rcd; //clk_activate
uvm_reg_field cas_latency;
uvm_reg_field t_refi;//cas_latency
uvm_reg_field t_rfc;//auto_refresh
uvm_reg_field t_wr;//clk_auto_refresh
function new(string name = "time_reg");
super.new(name,28,build_coverage(UVM_NO_COVERAGE));
endfunction
virtual function void build();
t_rp = uvm_reg_field::type_id::create("t_rp");
t_rcd = uvm_reg_field::type_id::create("t_rcd");
cas_latency = uvm_reg_field::type_id::create("cas_latency");
t_refi = uvm_reg_field::type_id::create("t_refi");
t_rfc = uvm_reg_field::type_id::create("t_rfc");
t_wr = uvm_reg_field::type_id::create("t_wr");
t_rp.configure(this,2,0,"RW",1,2'h2,1,1,0);
t_rcd.configure(this,3,3,"RW",1,3'h2,1,1,0);
cas_latency.configure(this,6,0,"RW",1,6'h0,1,1,0);
t_refi.configure(this,11,7,"RW",1,11'h2E4,1,1,0);
t_rfc.configure(this,4,18, "RW",1,4'h8,1,1,0);
t_wr.configure(this,2,22,"RW",1,2'h1,1,1,0);
endfunction
endclass
class delay_reg extends uvm_reg;
`uvm_object_utils(delay_reg)
// uvm_reg_field rst_dely;
uvm_reg_field inc_dec_dely;
uvm_reg_field tap_delay;
uvm_reg_field phas_dqs;
uvm_reg_field inc_dec_phas_dqs;
uvm_reg_field dqs_rdy_phas;
uvm_reg_field pll_stat;
function new(string name = "delay_reg");
super.new(name,17,build_coverage(UVM_NO_COVERAGE)); //26+1+1+1+64+64
endfunction
virtual function void build();
// rst_dely = uvm_reg_field::type_id::create(“rst_dely”);
inc_dec_dely = uvm_reg_field::type_id::create(“inc_dec_dely”);
tap_delay = uvm_reg_field::type_id::create(“tap_delay”);
phas_dqs = uvm_reg_field::type_id::create(“phas_dqs”);
inc_dec_phas_dqs = uvm_reg_field::type_id::create(“inc_dec_phas_dqs”);
dqs_rdy_phas = uvm_reg_field::type_id::create(“dqs_rdy_phas”);
pll_stat = uvm_reg_field::type_id::create(“pll_stat”);
// rst_dely.configure(this,0,0,"WO",1,1'h0,1,1,0);
inc_dec_dely.configure(this,1,0,"WO",1,1'h0,1,1,0);
tap_delay.configure(this,2,0,"WO",1,2'h0,1,1,0);
phas_dqs.configure(this,3,0, "WO",1,3'h0,1,1,0);
inc_dec_phas_dqs.configure(this,4,0,"WO",1,4'h0,1,1,0);
dqs_rdy_phas.configure(this,5,0,"RO",1,5'h0,1,1,0);
pll_stat.configure(this,2,6,"RO",1,2'h0,1,1,0);
endfunction
endclass
class hpdmc_reg_block extends uvm_reg_block;
`uvm_object_utils(hpdmc_reg_block)
rand sys_reg sys_r;
rand bypass_reg bypass_r;
rand time_reg time_r;
rand delay_reg delay_r;
uvm_reg_map csr_map; // Block map
uvm_reg_map fml_map; // Block map
uvm_reg_map sdram_map; // Block map
uvm_reg_map dqs_map; // Block map
function new(string name = "hpdmc_reg_block");
super.new(name, build_coverage(UVM_CVR_ADDR_MAP));
endfunction
virtual function void build();
string s;
sys_r = sys_reg::type_id::create(“sys_r”);
sys_r.configure(this, null,“”);
sys_r.build();
for(int i = 0; i < 3; i++) begin
$sformat(s, “sys_r[%0d]”, i);
sys_r.add_hdl_path_slice(s, i, 1);
end
bypass_r = bypass_reg::type_id::create(“bypass_r”);
bypass_r.configure(this, null, “”);
bypass_r.build();
for(int i = 0; i < 21; i++) begin
$sformat(s, “bypass_r[%0d]”, i);
bypass_r.add_hdl_path_slice(s, i, 1);
end
time_r = time_reg::type_id::create(“time_r”);
time_r.configure(this, null, “”);
time_r.build();
for(int i = 0; i < 28; i++) begin
$sformat(s, “time_r[%0d]”, i);
time_r.add_hdl_path_slice(s, i, 1);
end
delay_r = delay_reg::type_id::create(“delay_r”);
delay_r.configure(this, null, “”);
delay_r.build();
for(int i = 0; i < 17; i++) begin
$sformat(s, “delay_r[%0d]”, i);
delay_r.add_hdl_path_slice(s, i, 1);
end
fml_map = create_map("fml_map", 'h0, 4, UVM_LITTLE_ENDIAN);
fml_map.add_reg(sys_r, 32'h00000000, "RO");
fml_map.add_reg(bypass_r, 32'h00000004, "RW");
fml_map.add_reg(time_r, 32'h00000008, "RW");
fml_map.add_reg(delay_r, 32'h0000000C, "RW");
add_hdl_path("top.dut.u4", "RTL");
lock_model();
endfunction
endclass
Runtime Errors :
include_coverage not located