In reply to muneebullashariff:
Quote:
In reply to dave_59:
Quote:
In reply to muneebullashariff:
Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog?
Hi Dave,
Many thanks for your reply.
I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM.
In which language should I code my reference model:
Using C or
Using SV
Furthermore, what is the best way to verify the reference model?
Regards,
Muneeb
Apart from what other members here have mentioned, keep also in mind that a reference model is expected to be a model against which you would conclude whether the DUT is correct or not.
Now, the features can themselves be temporal by nature.
If this is the case and any of the following is true then you are better off using SV for modelling:
1) you want to verify the temporal behaviour of the DUT
2) you have no other way to verify the temporal behaviour other than modelling it in reference model. For example, transactional level temporal checks can be easily done using assertions and should be the first choice. Deep sequential behaviour are hard to be captured using assertions. So, these will be mostly done in SV
Please also be aware that a reference model need not be monolithic. In fact, it is common to accomplish overall reference model behaviour using "sum of parts" approach. Meaning, many reference models can be combined to get the overall behaviour. So, you can have some in C++ domain and some in SV domain depending on all the above criteria mentioned above and by other members here.
