Recording a Class Variable in Questasim

UVM
,
1

Hi,

If there is any way to dump the class variable in QuestaSim for UVMEnviroment.
Before we use Cadence to dump all the class variable in UVMEnviroment.
Similar way if it is possible to dump all the class variable in Questasim.

Regards
Elango.V

2

Yes, but Questa does not dump classes by default.

See these two sections in the Questa User Manual

SystemVerilog Class Debugging

UVM-aware Debugging

3

In reply to dave_59:

An approach that is tool independent is to copy the desired class variables into a SV interface, which could be either an existing interface or a dedicated one for debug. The copying can be done through a task call.
I used that technique in the past.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115