Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
UVM
  • Home
  • Forums
  • UVM
  • Recommended UVM scoreboard architecture

Recommended UVM scoreboard architecture

UVM 6753
uvm 124 scoreboard 22 architecture 3 predictor 3 comparator 8
Paul McKechnie
Paul McKechnie
Full Access
6 posts
July 09, 2015 at 9:09 am

As I understand the architecture of a scoreboard, it should consist of a single predictor and a comparator, where the predictor receives a sequence of transactions on a single analysis port. The predictor then creates the next expected transaction, which is passed to the comparator for evaluation.

How should the predictor be designed when the state of the DUT needs to be modelled using two or more analysis ports?

My design has two interfaces, which work with distinct transaction types. The first receives a sequence of packets and generates responses. The second alters the mode of the DUT, which naturally affects the values of the responses generated on the first interface. Is it appropriate to add an additional analysis port to the predictor to cope with this scenario? Or is there another technique that I am not aware of yet?

Replies

Log In to Reply
Tudor Timi
Tudor Timi
Full Access
333 posts
July 09, 2015 at 9:27 am

In reply to Paul McKechnie:

The picture you are talking about (one stream, predictor, comparator) is more a theoretical one. In real life you'll rarely have a DUT that works like that. In your case you'll definitely need another way of getting information to your predictor.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

Paul McKechnie
Paul McKechnie
Full Access
6 posts
July 09, 2015 at 11:22 pm

In reply to Tudor Timi:

Perhaps my question should be rephrased as, are there any examples of how the scoreboard is actually implemented in real designs? What properties of the scoreboard are invariant and what can be changed to suit the needs of the design under test without deviating from the UVM approach?

Tudor Timi
Tudor Timi
Full Access
333 posts
July 13, 2015 at 1:22 am

In reply to Paul McKechnie:

I don't think there's much literature available on the topic. You could probably find some examples in the Verification Academy cookbooks, but even there it'll probably limited to a device that takes input through one interface and outputs something through another interface (like the classical router example you find in most books).

There aren't many resources available online, as companies aren't eager to share code. The lack of free tools also doesn't help, because it discourages hobby projects from popping up.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

Paul McKechnie
Paul McKechnie
Full Access
6 posts
July 13, 2015 at 2:11 am

In reply to Tudor Timi:

Indeed, I think that you have hit the nail on the head. I have been using the cookbooks to improve my understanding of UVM and its architecture but I have found them somewhat light on the topic of scoreboards. The examples all show a single analysis port but do not suggest how it would scale for larger designs. One of the webinars that I watched regarding scoreboards also suggested that a predictor should only have a single analysis port. Hence the confusion.

Tudor Timi
Tudor Timi
Full Access
333 posts
July 13, 2015 at 2:15 am

In reply to Paul McKechnie:

For more stubborn designs you're probably going to need every trick in the book: integrate your prediction components with your register models, maybe even add some references to signals (gasp!). I find that TLM purism is a bit too widespread.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

Phill_Ferg
Phill_Ferg
Full Access
69 posts
July 14, 2015 at 12:57 am

In reply to Tudor Timi:

Bear in mind a scoreboard is just a comparator - what you compare is up to you. A predictor may suit or perhaps interface equivalence checking is all you need.

Over the years i have found that scoreboard architectures have adapted to the dut. E.g. i was once looking at a abstracted memory controller with 100's of ports. I could have created a huge scoreboard, but in this case lots of little ones server the purpose with greater reuse. I have also had scoreboards with lots of analysis ports (mostly analysis fifos to decouple data from the monitors) juggling lots of comparisons

I have always found that a significant amount of scoreboard time is spent decomposing and reforming sequence_items into a common format. Some times this has been an independent easily comparable format, other times i have used the do_compare() from one of the sequence_items.

Register models are a curious case because of the UVM format used to update the register model - in this scenario my predictor and adaptors are always housed with the rest of my UVC components, well away from the scoreboard.

My answer follows your initial train of thought. Either create a configurable predictor for all DUT modes or create multiple predictors dependent on the mode of the DUT you wish to replicate. Where you put the analysis port is up to you. If you want to reuse the predictor then perhaps multiple predictors is best and allow the scoreboard to route the incoming data?
I assume your "configuration" interface is trivial enough that your could create a uvm_monitor or route the sequence_items direct from the driver. This then leads onto if you are verifying how the DUT responds to silly things on the "configuration" interface.

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA