Receiving a wrong transaction to bus2reg function in uvm_adapter

My register block has two differnt interfaces. In RAL environment, created separate Register map for each interface. Reg adapters also created according to the interface. Let’s assume adpater_1 for interface_1 and adapter_2 for interface_2.
In this case, when we are trying to access registers from both the interfaces, only sometimes the bus2reg function in adapter_2 is receiving response packet corresponds to Interface_1. What could be the reason ?

In reply to kishore_tavva:

Without seeing more code it is impossible to give you an advice. But it looks like you do not have a clean and seperated environment with respect to the interfaces.

In reply to chr_sue:

Hi,
Please find the pseudo code below.


class user_reg_block extends uvm_reg_block;

    //SFR's in the register block. Each register is 32 bits.
	rand user_sfr_a  sfr_a;
	rand user_sfr_b  sfr_b;
	
	//Two register maps declared for two interfaces intf_1 and intf_2
	uvm_reg_map map_intf_1;
	uvm_reg_map map_intf_2;
	
	virtual function void build();
		//Create the registers
		sfr_a = user_sfr_a::type_id::create("sfr_a");
		sfr_a.configure(this,null,"");
		sfr_a.build();
		
		sfr_b = user_sfr_b::type_id::create("sfr_b");
		sfr_b.configure(this,null,"");
		sfr_b.build();
		
		//Create the maps and add the registers into its map
		this.map_intf_1 = create_map("map_intf_1",32'h0, 'h4,UVM_LITTLE_ENDIAN,1);
        this.map_intf_2 = create_map("map_intf_2",32'h0, 'h4,UVM_LITTLE_ENDIAN,1);

		this.map_intf_1.add_reg(sfr_a, 32'h0, "RW");
		this.map_intf_1.add_reg(sfr_b, 32'h4, "RW");
		this.map_intf_2.add_reg(sfr_a, 32'h0, "RO");
		this.map_intf_2.add_reg(sfr_a, 32'h4, "RW");

	endfunction
endclass

// For the driver on interface 1 -> Req packet is of type packet_x and response is of type packet_y
class driver_intf_1 extends uvm_driver#(packet_x, packet_y);

endclass : driver_intf_1

// For the driver on interface 2 -> Both REQ and RSP is of type packet_z
class driver_intf_2 extends uvm_driver#(packet_z, packet_z);

endclass : driver_intf_2

class intf_1_adapter extends uvm-reg_adapter;
    `uvm_objcet_utils(intf_1_adapter);
	
	function new(stringg name = "intf_1_adapter")
		super.new(name);
		supports_byte_enable = 0;
		provides_responses = 1;
	endfunction : new
	
	virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
		packet_x intf_1_pkt_h;
		// Form the packet from rw fields based on read or write command
		return intf_1_pkt_h;
	endfunction
	
	virtual function void bus2reg(uvm_sequence_item item, ref uvm_reg_bus_op rw);
		packet_y intf_1_rsp_pkt_h;
		
		if(!$cast(intf_1_rsp_pkt_h,bus_item))
			`uvm_fatal(get_type_name(),"NOT able to cast input transaction in bus2reg")
	endfunction
endfunction

class intf_2_adapter extends uvm-reg_adapter;
    `uvm_objcet_utils(intf_2_adapter);
	
	function new(stringg name = "intf_2_adapter")
		super.new(name);
		supports_byte_enable = 0;
		provides_responses = 1;
	endfunction : new
	
	virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
		packet_z intf_2_pkt_h;
		// Form the packet from rw fields based on read or write command
		return intf_2_pkt_h;
	endfunction
	
	virtual function void bus2reg(uvm_sequence_item item, ref uvm_reg_bus_op rw);
		packet_z intf_2_rsp_pkt_h;
		
		if(!$cast(intf_2_rsp_pkt_h,bus_item))
			`uvm_fatal(get_type_name(),"NOT able to cast input transaction in bus2reg")
	endfunction
endfunction

class custom_reg_env extends uvm_env;
	//Register block declaration
	user_reg_block  reg_block_h;
	
	//Adapter declaration
	intf_1_adapter adapter_1_h;
	intf_2_adapter adapter_2_h;
	
	//Predictor handles
	uvm_reg_predictor#(packet_y) predictor_1_h;
	uvm_reg_predictor#(packet_z) predictor_2_h;
	
	function new(string name = "custom_reg_env",uvm_component parent);
		super.new(name,parent);
	endfunction : new
	
	virtual function void build_phase(uvm_phase phase);
		super.build_phase(phase);
		reg_block_h = user_reg_block::type_id::create("reg_block_h",this);
		adapter_1_h = intf_1_adapter::type_id::create("adapter_1_h");
		adapter_2_h = intf_2_adapter::type_id::create("adapter_2_h");
		predictor_1_h = uvm_reg_predictor#(packet_y)::type_id::create("predictor_1_h");
		predictor_2_h = uvm_reg_predictor#(packet_z)::type_id::create("predictor_2_h");
		reg_block_h.build();
		reg_block_h.lock_model();
			
	endfunction
	
	virtual function void connect_phase(uvm_phase phase);
		predictor_1_h.map = reg_block_h.map_intf_1;
		predictor_1_h.adapter = adapter_1_h;
		
		predictor_2_h.map = reg_block_h.map_intf_2;
		predictor_2_h.adapter = adapter_2_h;
	endfunction
	
endclass

class virt_sequencer extends uvm_sequencer;
	intf_1_sequencer intf_1_seqr; //sequencer for driver on interface 1
	intf_2_sequencer intf_2_seqr; //sequencer for driver on interface 2
endclass

class final_tb_env extends uvm_env;
	`uvm_component_utils(final_tb_env)
	
	virt_sequencer  virt_seqr;
	custom_reg_env  reg_env_h;
	
	virtual function void build_phase();
		//Both agents are built for interface 1 and interface 2
		//Create the virtual sequencer handle
		reg_env_h = custom_reg_env::type_id::create("reg_env_h",this);
		
	endfunction
	
	virtual function void connect_phase(uvm_phase phase);
		super.connect_phase(phase);
		reg_env_h.reg_block_h.map_intf_1.set_sequencer(virt_seqr.intf_1_seqr,reg_env_h.adapter_1_h);
		reg_env_h.reg_block_h.map_intf_2.set_sequencer(virt_seqr.intf_2_seqr,reg_env_h.adapter_2_h);
		
	endfunction
	

endclass

In reply to kishore_tavva:

To get the right understanding:
(1) you have 2 different virtual interfaces and 2 agents.
(2) because you have 2 different agents you have also 2 different seq_items.
(3) Through both agents you are accessing different parts of your register model.

Is this correct?

In reply to chr_sue:

In reply to kishore_tavva:
To get the right understanding:
(1) you have 2 different virtual interfaces and 2 agents.
(2) because you have 2 different agents you have also 2 different seq_items.
(3) Through both agents you are accessing different parts of your register model.
Is this correct?

Yes chr_sue, your understanding is correct.

In reply to kishore_tavva:

What does it mean 'a wrong transaction? Dou mean a wrong transaction type or a transaction with invalid content?