Reason behind generating clock in top module

UVM
1

Why should we generate clock in top module alone and not anywhere else like interface or some other blocks? What happens if I declare clock in some other block apart from top module.

module top;
   
  //clock and reset signal declaration
  bit clk;
  bit reset;
   
  //clock generation
  always #5 clk = ~clk;
   
  //reset Generation
  initial begin
    reset = 1;
    #5 reset =0;
  end
   
  //creatinng instance of interface, inorder to connect DUT and testcase
  mem_if intf(clk,reset);
   
  //DUT instance, interface signals are connected to the DUT ports
  memory DUT (
    .clk(intf.clk),
    .reset(intf.reset),
    .addr(intf.addr),
    .wr_en(intf.wr_en),
    .rd_en(intf.rd_en),
    .wdata(intf.wdata),
    .rdata(intf.rdata)
   );
   
  initial begin
    run_test();
  end
endmodule
2

In reply to jwl1806:

I have not heard of such a rule. how to generate clock from the driver | Verification Academy

3

In reply to dave_59:

Ok.I want to rephrase the question now. Why should we generate a global clock signal in a static entity like module or interface? Why cant we generate clock in a class?