Reading a right value inside a uvm_driver

Hi,

I am driving a read trasaction to the DUT from the uvm_driver and RTL is such that as soon as I drive the address bus the read appears on the r_data in the same clock cycle. I am trying read back the data the same cycle but I am getting a value from the prvious cycle. As a workaround I am using @(negdge vif.clk); to read back the right value. Is there a better way to read the right value?

Answers are much appreciated thanks.

				
                         task drive_trans(packet_trans trans_mem);
                            ......
                             case(trans_mem.type)
                                 .....
                                MEM_RD :  begin
					vif.mem_tx.mem_en <= 1'b0;
					vif.mem_tx.mem_addr <=  trans_mem.mem_addr;
					
                                       //@(negedge vif.fast_clk);
				    
					**trans_mem.mem_read_data[trans_mem.mem_addr] = vif.mem_rdata;**
				       `uvm_info("READ_DATA",$sformatf("Value of mem data in the addr %0d is 
                                         %h",trans_mem.mem_addr,trans_mem.mem_read_data[trans_mem.mem_addr] ),UVM_LOW)
				  end
                          endtask  

In reply to Abhiman:
The correct behavior of most read operations is you put the address out one clock cycle and you get the data back the next.

In reply to dave_59:
Thanks Dave for your reply.