Reactive uvm testbench

UVM
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1

Hi,

When would we need reactive UVM testbenches?

This is the first time I am working with such a scenario.

I have a DUT which has a command fifo interface and based on the fifo input data to the DUT, DUT needs to request to read data from the Cache on a Cache request/Cache data interface.

DUT is controlled by a controller that looks at the data that is read from the cache and if it has an error, the controller decides to abort sending the command(no processing happens in the DUT) to the host.

My understanding is that in this case, since I would need to mimic the driving of 1) Command fifo interface 2) Cache request interface 3) Controller interface, I would need a reactive TB. Please share your inputs, if I am wrong also.

Could someone point me to a real world uvm example reactive testbench?

Thank you.

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In reply to UVM_learner6:

These reactive interfaces are also known as slave interfaces. See Sequences/Slave | Verification Academy for how o drive them.

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In reply to dave_59:

Thank you for the pointer Dave. Is my idea correct that in this DUT case, I would need a reactive TB or is there any way I can just do a proactive TB?

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In reply to UVM_learner6:

This is a typical usecase of DMA. In this scenario, DUT act as a DMA. It takes requests from the command interface. Issues a read transaction to Cache line and finally forward the read response to host controller. If host controller gets a wrong response, it stops command interface transactions.
Over here, DUT acts as a master. Reading transactions from cache, cache VIP act as a slave. Writing the read response to Host controller will be in Host controller memory which also requires a Slave VIP. At command interface, master VIP is required to issue command transfers.

So reactive agents will be the Cache slave VIP and host controller slave memory VIP.
I hope it answers your query.