When would we need reactive UVM testbenches?
This is the first time I am working with such a scenario.
I have a DUT which has a command fifo interface and based on the fifo input data to the DUT, DUT needs to request to read data from the Cache on a Cache request/Cache data interface.
DUT is controlled by a controller that looks at the data that is read from the cache and if it has an error, the controller decides to abort sending the command(no processing happens in the DUT) to the host.
My understanding is that in this case, since I would need to mimic the driving of 1) Command fifo interface 2) Cache request interface 3) Controller interface, I would need a reactive TB. Please share your inputs, if I am wrong also.
Could someone point me to a real world uvm example reactive testbench?