Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
      • Webinar Calendar

    • On-Demand Webinars

      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • All On-Demand Webinars

    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings

    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
Ask a Question
UVM
  • Home
  • Forums
  • UVM
  • Reactive agent for memory storage

Reactive agent for memory storage

UVM 5685
#uvm 251 #reactive agent 1 #sequence 22
UVM_SV_101
UVM_SV_101
Full Access
59 posts
June 26, 2020 at 1:47 pm

Hi,

I have designed an reactive slave as memory storage component. It simple stores data at specified addr with write and read commands. Since I am running the sequence in forever loop. How do I end the simulation?

class mem_sequence extends uvm_sequence #(mem_seq_item);
 
   `uvm_object_utils(mem_sequence)
 
   mem_sequencer p_sequencer;
 
   function new(string name="mem_sequence");
      super.new(name);
   endfunction
 
   task pre_body();
      $cast(p_sequencer,m_sequencer);
   endtask
 
   task body();
      mem_seq_item m_item;
      mem_seq_item m_req;
      forever begin
 
         p_sequencer.m_req_fifo.get(m_req);
 
         if(m_req.write == 1)begin
           `uvm_do_with(m_item, {m_item.ack ==1; m_item.read==0;});
         end
         if(m_req.read == 1)begin
           `uvm_do_with(m_item, {m_item.ack ==1; m_item.data_in == m_req.data_in; m_item.write==0; m_item.read==1;});
         end
      end
   endtask
 
 
endclass

Replies

Log In to Reply
dave_59
dave_59
Forum Moderator
8753 posts
June 26, 2020 at 4:36 pm

In reply to ak_verifsj:

Objections is how the UVM ends the test. All threads get killed when there are no more objections to the run_phase. See https://verificationacademy.com/cookbook/endoftest

— Dave Rich, Verification Architect, Siemens EDA

dnguyen82us
dnguyen82us
Full Access
17 posts
June 28, 2020 at 6:34 pm

In reply to dave_59:

Assume that your sequence is started in main phase, the test can query the scoreboard in the environment to know when all the responses to the stimulus have come out of the DUT and drop the objection for the phase in order to move to the next phase. When this occurs, your sequence is killed automatically as Dave pointed out.

n347
n347
Full Access
40 posts
June 28, 2020 at 7:04 pm

In reply to dnguyen82us:

How do you query the scoreboard to know when all the responses to the stimulus has come out?
Not sure how to do this? like some event?

dnguyen82us
dnguyen82us
Full Access
17 posts
June 28, 2020 at 7:31 pm

In reply to n347:

Example:

virtual task main_phase(...);
starting_phase.raise_objection();
wait (env.scoreboard.act_number_of_responses == config.number_of_reads);
starting_phase.drop_objection();
endtask : main_phase

PS: there are several sources to get the number of reads from (scoreboard or configuration), scoreboard is basically the sink of all stimulus and response transactions

n347
n347
Full Access
40 posts
July 12, 2020 at 8:49 am

In reply to ak_verifsj:

How is this a memory storage? i see it as a reactive slave sending responses (ack) to the DUT.

How were you able to end the test?

dnguyen82us
dnguyen82us
Full Access
17 posts
July 18, 2020 at 2:14 pm

In reply to n347:

In your sequencer, you have a handle to a memory model.

voraravi
voraravi
Full Access
25 posts
July 19, 2020 at 2:43 am

[i]In reply to ak_verifsj:

you should execute all the sequences that have forever loop in its body method inside fork... join_none.

class axi_rand_burst_transfer extends axi_base test;
    ...
    ...
    task run_phase(uvm_phase phase);
 
        ...
        ...
        phase.raise_objection(this);
        fork
            slave_seq.start(axi_slave_sequencer);    //run the slave_seq that has forever  
        join_none                                    //loopinside fork_none
 
        //execute other sequences normally
        axi_rand_burst_seq.start(axi_master_seqr);
        phase.drop_objection(this);
        ...
        ...
    endtask
 
endclass
chr_sue
chr_sue
Full Access
3327 posts
July 19, 2020 at 4:48 am

In reply to voraravi:

I'm not sure if this is a good solution. Your env should have seoerate agents for slave and master. This is the common approach for master/slave systems.

dnguyen82us
dnguyen82us
Full Access
17 posts
November 28, 2020 at 11:13 am

In reply to chr_sue:

You only need to implement one agent for each interface. The agent instantiates appropriate components based on a configuration knob that specifies it's in master or slave mode.

Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy