Hi
I am trying to reach a signal in my design in order to extract its data
//write to file
m_file = $fopen("mem_file", "w");
if(!m_file) begin
`uvm_error( get_type_name(), "File could not open")
end else
for (int i = 0; i < 256; i++) begin
mem [i]= top.AL_0.DUV.DIVO_FLOATINGPOINT_V12_0_INST.DMEM_INT.TTSDN65LPA256X38M4F_I.MX.mem[i];
$fwrite (m_file, " mem [%0d] = %0d",i,mem [i]);
end
$fclose(m_file);
end
However nothing is written.
when I open the fine it is empty so I suppose that it could not reach the mem
In reply to mariam triki:
Are you sure your hierarchical path is correct? Please double-check.
Your $fwrite is not complete. You are writing the index only but not the memory content.
See the example below. This shows how you should implement your code:
module top;
logic [7:0] mem [0:255];
int m_file;
initial begin
for (int i = 0; i < 256; i++)
mem [i] = i+2;
m_file = $fopen("mem_file", "w");
if(!m_file) begin
//`uvm_error( get_type_name(), "File could not open")
$display("File could not be opened");
end else begin
for (int i = 0; i < 256; i++) begin
// mem [i]= top.AL_0.DUV.DIVO_FLOATINGPOINT_V12_0_INST.DMEM_INT.TTSDN65LPA256X38M4F_I.MX.mem[i];
$fwrite (m_file, "mem [%0d] = %0h\n",i, mem[i]);
$display ("mem [%0d] = %0h",i, mem[i]);
end
$fclose(m_file);
end
end
endmodule
In reply to chr_sue:
I have already found out about the memory content so I have edit it.
I am sure about the hierarchical path since I have already used for reading op.
Previously I run my test at the beginning
run_test();
m_file = $fopen("mem_file", "w");
.
.
$fclose(m_file);
the mem_file is empty
but when I put
run_test();
at the end (After $fclose(m_file)) I got these values
mem [1] = 0
mem [2] = 0
mem [3] = 0
mem [4] = 0
mem [5] = 0
mem [6] = 0
mem [7] = 0
mem [8] = 0
mem [9] = 0
mem [10] = 0
mem [11] = 0
In reply to mariam triki:
run_test() does not run your test. In the UVM you are instantiating your test class in the toplevel module. The test defined by +UVM_TESTNAME will be executed when you are starting your test.
With $fclose the content from the memory in your simulator will be put to the file.
In reply to chr_sue:
I am starting my test by providing the UVM_TESTNAME command line argument:
in the waveform mem [i] is different than “0”
that is why I think that the prob is with reaching the mem signal
Really I still can’t figure out the UVM !! I hope that I will get to see the whole picture soon enough
In reply to mariam triki:
You can try using uvm_hdl_read
uvm_hdl_read(signal, hdl_read_value)
//Definition in the uvm class reference.
uvm_hdl_read()
import "DPI-C" context function int uvm_hdl_read(
string path,
output uvm_hdl_data_t value
)
//Gets the value at the given path. Returns 1 if the call succeeded, 0 otherwise
In reply to chr_sue:
Hi
My colleague used a container to reach the signal and it worked fine
but I don’t understand why ;
virtual dMEM_V6_oom_ref_if dmem_vif;
vif_container#(virtual dMEM_V6_oom_ref_if) dmem_vif_container;
...
virtual function void build_phase(uvm_phase phase);
...
dmem_vif = dmem_vif_container.get_v_if("dMEM_V6_oom_ref_if");
..
endfunction: build_phase
...
task run_phase(uvm_phase phase);
....
for (int i = 0; i < 1024; i++) begin
file_name = $psprintf("dumpfile_dmem_%0d", i);
m_file = $fopen(file_name, "w");
if(!m_file) begin
`uvm_error(get_type_name(), "File could not open")
end
for (int j = 0; j < 256; j++) begin
$fwrite(m_file, "%h\n", dmem_vif.mem[j][31:0]);
end
$fclose(m_file);
end
....
She don’t speak English so unfortunately she can not explain it to me.
Please can you give me an explanation.
In reply to mariam triki:
So far you did not say your meme is part of your virtual interface. If this is the case then it is just easy, even without using the uvm_container.
In your case the container encapsulates the virtual interface. This allows you to make a refence in any place you need this container with the interface. The more common solution is to put your virtual interface to the config_db and retrieve itt in the place where you need it.
In reply to chr_sue:
I did as you suggested.
I need to use mem from the dmem_vif
and Enable_uA ,Startup_complete from the other interface but when I run the simulation I got this Error
“Error: uninitialized virtual interface object” and it points to “divo_vif.Startup_complete”
virtual DIVO_FloatingPoint_V12_0_oom_ref_if divo_vif;
virtual dMEM_V6_oom_ref_if dmem_vif;
virtual function void build_phase(uvm_phase phase);
...
uvm_config_db#(virtual dMEM_V6_oom_ref_if)::set(null,"*","dmem_vif",dmem_vif); //set method
uvm_config_db#(virtual DIVO_FloatingPoint_V12_0_oom_ref_if)::set(null,"*","divo_vif",divo_vif);
endfunction: build_phase
task run_phase(uvm_phase phase);
...
if( !uvm_config_db#(virtual dMEM_V6_oom_ref_if)::get(this,"*", "dmem_vif", dmem_vif))
`uvm_fatal(get_full_name(),{"virtual interface must be set for:",".dmem_vif"} ); //get method
if( !uvm_config_db#(virtual DIVO_FloatingPoint_V12_0_oom_ref_if)::get(this,"*", "divo_vif", divo_vif))
`uvm_fatal(get_full_name(),{"virtual interface must be set for:",".divo_vif"} ); //get method
...
wait(divo_vif.Startup_complete);
for (int i = 0; i < 1024; i++) begin
file_name = $psprintf("file_dmem_%0d", i);
m_file = $fopen(file_name, "w");
end
for (int i = 0; i < 256; i++) begin
wait (divo_vif.Enable_uA) ;
wait (!divo_vif.Enable_uA) ;
//write to file
$fwrite (m_file, "%0d \n ",dmem_vif.mem[i]);
$fclose(m_file);
end
In reply to mariam triki:
Probably, root cause of the issue (got all value in mem[i] as 0) is that you misunderstand
when $fopen and $write are executed.
At first, all codes after run_test() never executed because $finish is called in run_test().
initial begin
run_test();
m_file = $fopen("mem_file", "w");
.....
$fwrite (m_file, " mem [%0d] = %0d",i,mem [i]);
$fclose(m_file);
end
If you add codes before run_test(), mem[i] at time 0 are stored in the file.
This is because run_test() must execute at time 0, else return an error.
If you want to dump values of mem[i] to a file during simulation, you should write the code
in run_phase in uvm_monitor or uvm_driver.
If you want to dump it at end of simulation, it is good to write the code in
- final block in testbench module.
- report_phase function in uvm_monitor or uvm_driver.
In reply to mariam triki:
I’m not sure if it is a good idea to have your memory in the SystemVerilog interface. But if you believe you want to do this than it is as it is.
Using the virtual interface approach with the config_db requires that you are doing a set to the config_db in the toplevel module of your UVM testbench. Then you can perform in any other component which needs this interface can preform a get.