Randomization phases in uvm

UVM
1

hi,
why we do randomization in run phase?
why cant we do in build phase or any other phases?
please explain me clearly
regards,
durga bhargav

2

In reply to durga bhargav:

There is no such restriction. The only place you cannot do randomization is in the compilation of your code, like a parameter setting the width of a variable declaration.

3

In reply to dave_59:

There are no restrictions as where to place code for randomization. However there are concepts called:

  1. Early Randomization and
  2. Late Randomization*.

*From a book “Cracking Digital VLSI Verification Interview”.

Early Randomization is what usually happen in build_phase() which I don’t think serves any advantage, but disadvantage here is if later on testbench drops/kills randomized object then this randomization effort by the tool goes waste. Also you could see initial slowing down of simulation during 0ns time if all randomization is done at initial stage only.

Late Randomization is achieved by calling randomize() just before that random set of data is required.

Sometimes these things does not make a lot of improvements but taking care of details when coding large testbench saves time & system memory!

4

In reply to MayurKubavat:

The key question is what do you wnt to randomize. If you want to randomize pattern it does not make any sense doing this in the build_phase.
But if you want to randomize a configuration pbject which takes influence on your testbench it makes really sense.
I’m not sure if ‘Early Randomization’ and ‘Late Randomization’ makes really sense.