In reply to mitesh.patel:
It is broken: https://verificationacademy.com/forums/uvm/uvmregfifo-broken
And from the UVM bug tracking system:
0006952: uvm_reg_fifo is fully broken..
I am writing to report a fairly large issue with uvm_reg_fifo.svh which makes it unusable.
the use model for the fifo is the following:
1) create reg_fifo of depth n
2) do a set() to add values to fifo. A check in set() ensures filling fifo till it is full and discarding after that.
3) fifo.update() to flush the values to the rest of register model and update the DUT.
uvm_reg_fifo extends from uvm_reg. The set() in uvm-reg is virtual
so, the set() method in uvm_reg_fifo overrides the implementation in uvm_reg.
when fifo.update() is called, the update() method calls write() which then calls set() which then goes back to uvm_reg_fifo and adds another entry to the fifo queue. (duplicated basically)
This repeats till the fifo fills up, regardless of how deep the fifo is.
The end result is that you see as many transactions on the bus adapter as there are entries. for example if the fifo is 8 deep, and you did 4 set() calls, you will still see 8 transactions on the bus.
The fix is to do a check of m_is_update_pending member from the uvm_reg base class before appending to the fifo (1 line fix) which is set to 1 if an update() is in progress in the set() method in uvm_reg_fifo.
That will prevent the fifo from filling up.