There are set_access and set_reset method of uvm_reg_field that you can use to change the model at run time. You cannot add/delete a register/memory once it is locked.
Explicit prediction means the RAL model gets updated by observing bus transactions using the uvm_reg_predictor component. Passive or implicit prediction updates the RAL model directly from the read/write methods.
Explicit prediction I understood. Can you please elaborate more about implicit prediction? If implicit prediction updates mirrored value on write and read methods, then what is the difference between auto prediction and passive prediction?
As per my understanding, auto prediction updates mirror value only if we configure set_auto_predict(1). Is it correct understanding?
This is an area where I don’t have much experience. “Passive Prediction” is not a standard mode in the UVM RAL, but I think this is a use model where explicit prediction happens when there is bus activity not created directly by a UVM_reg action like a read or write.
I have a question related to RAL usage for verifying the veracity of the RTL registers.
Generally, the registers’ definition is written in Excel sheet or SystemRDL. Then from this single source, various items are derived/created:
RTL for registers
UVM RAL
If there is an error while creating the register spec(definition) then that would propagate to both RTL and RAL. For example, the register’s reset value is 0x3333 but while entering the value in register Spec there was an error and value entered is 0x1000.
Since this error has propagated to both RTL and RAL how can we figure out this error?