RAL read and write issues to Design

UVM
, ,
1

Hello

I have integrated my UVM RAL into the existing TB and was able to have the connections and access to the reg_model.

Built-in env and in connect phase have done as shown below

  m_pcie_rm.default_map.set_sequencer(m_apbm_env[i].m_agent.sequencer,this.reg2apb);

When I run the sequence as shown below

m_pcie_rm.DWC_PCIE_USP_PF2_SRIOV_CAP_DBI2.SRIOV_BAR0_MASK_REG.read( .status(status),.value(r_val),.parent(this));

m_pcie_rm.DWC_PCIE_USP_PF2_SRIOV_CAP_DBI2.SRIOV_BAR0_MASK_REG.write(.status(status),.value(32'h8),.parent(this));

m_pcie_rm.DWC_PCIE_USP_PF2_SRIOV_CAP_DBI2.SRIOV_BAR0_MASK_REG.read(.status(status),.value(r_val),.parent(this));

The adapter values show read data as 0 and while write it shows 8. I have tried mirror check it too gives zero as its value despite write and I have observed desired getting updated with the write data 8 .


UVM_INFO    |   5336ns |                   apb_adapter.sv |   42 | reporter                                 | apb_adapter          | ADAPTER...
UVM_INFO    |   5336ns |                   apb_adapter.sv |   44 | reporter                                 | apb_adapter          | reg2bus addr=320224 data=0
UVM_INFO    |   5336ns |                   apb_adapter.sv |   42 | reporter                                 | apb_adapter          | ADAPTER...
UVM_INFO    |   5336ns |                   apb_adapter.sv |   44 | reporter                                 | apb_adapter          | reg2bus addr=320224 data=8
UVM_INFO    |   5336ns |                   apb_adapter.sv |   42 | reporter                                 | apb_adapter          | ADAPTER...
UVM_INFO    |   5336ns |                   apb_adapter.sv |   44 | reporter                                 | apb_adapter          | reg2bus addr=320224 data=0
UVM_INFO    |   5336ns |       cdv_cdns_pcie_vseq_base.sv |  301 | reporter@@pcie_cfg                       | cdns_pcie_cfg_vseq   | INSIDE RAL SEQ WORKING
UVM_INFO    |   5336ns |       cdv_cdns_pcie_vseq_base.sv |  304 | reporter@@pcie_cfg                       | cdns_pcie_cfg_vseq   | desired_val:8 
UVM_INFO    |   5336ns |       cdv_cdns_pcie_vseq_base.sv |  307 | reporter@@pcie_cfg                       | cdns_pcie_cfg_vseq   | desired_val:8 and r_val 0
UVM_ERROR   |   5336ns |       cdv_cdns_pcie_vseq_base.sv |  308 | reporter@@pcie_cfg                       | ERROR                | TEST FAILED
UVM_INFO    |   5336ns |                   apb_adapter.sv |   42 | reporter                                 | apb_adapter          | ADAPTER...
UVM_INFO    |   5336ns |                   apb_adapter.sv |   44 | reporter                                 | apb_adapter          | reg2bus addr=320224 data=0


Register "m_pcie_rm.DWC_PCIE_USP_PF2_SRIOV_CAP_DBI2.SRIOV_BAR0_MASK_REG" value read from DUT (0x0000000000000000) does not match mirrored value (0x00000000000fffff)

First adapter info is read then write and read . The last info is from mirror check . Is it the problem in agents in TB or my fault in RAL

2

In reply to Sv-hustler:

I have not used predictor so the mirrored value remains what it is from the spec and it matches. Don’t know why DUT got updated to 'h00000 instead of having default reset values if WRITE has not been performed

3

In reply to Sv-hustler:

You should check your reg2bus function. It looks like there is the problem. And we do not see any bus2reg when you are reading.

4

In reply to chr_sue:


class apb_adapter extends uvm_reg_adapter;
     `uvm_object_utils(apb_adapter)

   function new(string name ="apb_adapter");

       super.new(name);
       supports_byte_enable = 0;
       provides_responses = 0;
     
 
  endfunction



  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
       apbTransaction pkt = apbTransaction::type_id::create("pkt");
      
       

       pkt.Direction = (rw.kind == UVM_WRITE) ? APB_DIRECTION_WRITE :APB_DIRECTION_READ;
       pkt.Addr = rw.addr;
     //pkt.pwdata = (rw.kind == UVM_WRITE)?rw.data:pkt.pwdata;
      // if(rw.kind == UVM_WRITE) begin   
            pkt.Data = rw.data;
     //  else    
         //   pkt.prdata = rw.data;
     //  end


    //  if(rw.kind == UVM_READ) begin 
        //  pkt.Data = rw.data;
    // end 
        `uvm_info(get_type_name(),"ADAPTER...",UVM_NONE)  
 
       `uvm_info(get_type_name(),$sformatf("reg2bus addr=%0h data=%0h",pkt.Addr,pkt.Data),UVM_NONE) 
      return pkt;
   endfunction


  virtual function void bus2reg (uvm_sequence_item bus_item,ref uvm_reg_bus_op rw);


    apbTransaction  pkt;
    


    if(!$cast(pkt,bus_item)) begin 
             `uvm_fatal ("reg2apb_adapter","Failed to cast bus_item to pkt")
    end 

  
   rw.kind = pkt.Direction ==APB_DIRECTION_WRITE ? UVM_WRITE : UVM_READ;
   rw.addr = pkt.Addr;
   rw.data = pkt.Direction ==APB_DIRECTION_WRITE ?pkt.Data:pkt.Data;
   rw.status =UVM_IS_OK;
     `uvm_info ("adapter",$sformatf("bus2reg : addr=0x%0h data=0x%0h kind=%s status=%s",rw.addr,rw.data,rw.kind.name(),rw.status.name()),UVM_DEBUG)
  endfunction
endclass

This is my adapter. Don’t know why bus2reg doesn’t work

5

In reply to Sv-hustler:

What are the commands on the physical interface to READ/WRITE?
Did you check your DUT regs were really written?
And when you start with a READ you do not know what the content of your reg was.

6

In reply to chr_sue:

I did not understand your first question. Are you referring to normal TB without RAL (How it does read and write)?>

Im new to verdi trying to check the registers . But as far as I know when I see the signals I dont see same values being driven . When I have done write I see data on prdata instead of pwdata .I will check the registers today and update

Yes I know the values from the design spec.

7

In reply to Sv-hustler:

When you are using a frontdoor acces this happens through the physical interface using read/write wrt to the physical interface.

8

In reply to chr_sue:

Ok . Is there any reason for bus2reg not being called at least once . I see most of the posts they are encountering is 2 calls to bus2reg. I have sued set_auto_predict

9

In reply to Sv-hustler:

To debug this is your turn. I do not see your code around.

10

The issue has been solved. The fix was just declaring the predictor explicitly instead of using auto_predict. Still don’t know why auto_predict fails to give the response back.