RAL-Null instance error

UVM
,
1

Hi,

I have question regading RAL Concept.

I have top Module now in the top module i’m instantiating my TIMER module and inside TIMER module one frctimer module is instantiated.
now i want to access the register “WdogLoad” inside the “frctimer” module.

class wdogload extends uvm_reg;
`uvm_object_utils(wdogload)
function new (string name=“wdogload”);
super.new(name,32,UVM_NO_COVERAGE);
endfunction
endclass

class wdog_reg_block extends uvm_reg_block;
`uvm_object_utils(wdog_reg_block)

wdogload load_reg;

uvm_reg_map wdog_map;

function new(string name=“wdog_reg_block”);
super.new(name,UVM_NO_COVERAGE);
endfunction

virtual function void build();

load_reg=wdogload::type_id::create(“WdogLoad”); //here what name i should give load_reg or “WdogLoad” which is given in rtl?
load_reg.configure(this,null,“”);
load_reg.add_hdl_path_slice(“frc”,0,32); //what path I should give? “frc” is the instance name of module frctimer
wdog_map=create_map(“wdog_map”,'h0,32,UVM_LITTLE_ENDIAN);

wdog_map.add_reg(load_reg,10’h0,“RW”);
add_hdl_path(“WDT”,“RTL”); // “WDT” is the instance name of my TIMER module in the top module?
lock_model();
endfunction
endclass

So, the path i have given is correct or wrong??
because it showing error int the sequence
->wdog_rb.load_reg.write(status,addr,wr_data,.map(wdog_rb.wdog_map),.parent(this));
“null instance occuring while derefrecing my sequence”// something like this

Thank you
Khushmit

2

In reply to Khushmit Pandya:

Hi Khushmit,

load_reg=wdogload::type_id::create(“load_reg”);
load_reg.add_hdl_path_slice(“frc”,0,32); // here you should write the name of register which is in RTL,not at the time of create
add_hdl_path(“WDT.fcr”,“RTL”); // try this out

Thanks,
sagar

3

In reply to sagar@aceic.com:

Hii Sagar,

Thank you for the solution.